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631
Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors
- In Proceedings of the 28th Annual International Symposium on Computer Architecture
, 2001
"... Hardly predictable data addresses in many irregular applications have rendered prefetching ineffective. In many cases, the only accurate way to predict these addresses is to directly execute the code that generates them. As multithreaded architectures become increasingly popular, one attractive appr ..."
Abstract
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Cited by 174 (0 self)
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applications, which is a 19% speedup over state-of-the-art software-controlled prefetching.
Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors
"... Hardly predictable data addresses in many irregular applications have rendered prefetching ineffective. In many cases, the only accurate way to predict these addresses is to directly execute the code that generates them. As multithreaded architectures become increasingly popular, one attractive appr ..."
Abstract
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applications, which is a 19% speedup over state-of-the-art software-controlled prefetching.
VSSAD/Alpha Development Group
"... Hardly predictable data addresses in man), irregular applica-tions have rendered prefetching ineffective. In many cases, the only accurate way to predict these addresses is to directly execute the code that generates them. As multithreaded architectures be-come increasingly popular, one attractive a ..."
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, which is a 19% speedup over state-of-the-art software-controlled prefetching. 1.
Design and Evaluation of a Compiler Algorithm for Prefetching
- in Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems
, 1992
"... Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefetching is useful in hiding the latency, issuing prefetches incurs an instruction overhead and can increase the load on the ..."
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Cited by 501 (20 self)
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Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefetching is useful in hiding the latency, issuing prefetches incurs an instruction overhead and can increase the load
Tolerating Latency Through Software-Controlled Prefetching in Shared-Memory Multiprocessors
- Journal of Parallel and Distributed Computing
, 1991
"... The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Although the provision of coherent caches in many recent machines has alleviated the problem somewhat, cache misses still occur frequently enough that they s ..."
Abstract
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Cited by 302 (18 self)
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that they significantly lower performance. In this paper we evaluate the effectiveness of non-binding software-controlled lyrefetching, as proposed in the Stanford DASH Multiprocessor, to address this problem. The prefetches are non-binding in the sense that the prefetched data is brought to a cache close
Compiler-Based Prefetching for Recursive Data Structures
- In Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems
, 1996
"... Software-controlled data prefetching offers the potential for bridging the ever-increasing speed gap between the memory subsystem and today's high-performance processors. While prefetching has enjoyed considerable success in array-based numeric codes, its potential in pointer-based applications ..."
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Cited by 203 (14 self)
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Software-controlled data prefetching offers the potential for bridging the ever-increasing speed gap between the memory subsystem and today's high-performance processors. While prefetching has enjoyed considerable success in array-based numeric codes, its potential in pointer
SoftwareControlled On-Chip Memory for High-Performance and
- Low-Power Computing,” Computer Architecture News
, 2002
"... The performance gap between processor and main memory speed, called memory wall, is serious problem especially in High Performance Computing (HPC). This memory wall problem is addressed by two factors, large memory access latency and lack of memory throughput. There have been proposed many technique ..."
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Cited by 3 (1 self)
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techniques for tolerating memory access latency, including cache prefetching. However, these techniques increase main memory traffic[1]. In order to overcome this problem, we have proposed a new processor architecture SCIMA (the abbreviation of Software Controlled Integrated Memory Architecture) which
The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems
, 1997
"... Current microprocessors aggressively exploit instructionlevel parallelism (ILP) through techniques such as multiple issue, dynamic scheduling, and non-blocking reads. Recent work has shown that memory latency remains a significant performance bottleneck for shared-memory multiprocessor systems built ..."
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Cited by 17 (5 self)
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built of such processors. This paper provides the first study of the effectiveness of software-controlled non-binding prefetching in sharedmemory multiprocessors built of state-of-the-art ILP-based processors. We find that software prefetching results in significant reductions in execution time (12
State-of-the-Art in Empirical Studies Authors:
"... Classification: public Software engineering processes depend on the context they are applied in. Thus, it is risky to determine the best processes for a given project context without empirical data from this context. This report summarizes important issues on the state of the art in empirical studie ..."
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Classification: public Software engineering processes depend on the context they are applied in. Thus, it is risky to determine the best processes for a given project context without empirical data from this context. This report summarizes important issues on the state of the art in empirical
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