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91
A Polynomial Spilling Heuristic: Layered Allocation
- Inria, July 2012, n o RR-8007, 23, http://hal.inria.fr/hal-00713693. References in notes
"... Register allocation is one of the most important, and one of the oldest compiler optimizations. It aims to map tempo-rary variables to machine registers, and defaults to explicit load/store from memory when necessary. The latter option is referred to as spilling. This paper addresses the minimizatio ..."
Abstract
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Cited by 2 (0 self)
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the minimization of the spill code overhead, one of the difficult problems in register allocation. We devised a heuristic, polynomial approach called layered. It is rooted in the recent advances in decoupled register allocation. As opposed to conventional incremental spilling, our method incrementally allocates
Spill Code Minimization via Interference Region Spilling
- in SIGPLAN Conference on Programming Language Design and Implementation
, 1997
"... Many optimizing compilers perform global register allocation using a Chaitin-style graph coloring algorithm. Live ranges that cannot be allocated to registers are spilled to memory. The amount of code required to spill the live range depends on the spilling heuristic used. Chaitin's spilling he ..."
Abstract
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Cited by 41 (1 self)
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Many optimizing compilers perform global register allocation using a Chaitin-style graph coloring algorithm. Live ranges that cannot be allocated to registers are spilled to memory. The amount of code required to spill the live range depends on the spilling heuristic used. Chaitin's spilling
Coloring heuristics for register allocation
- In PLDI ’89: Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
, 1989
"... We describe an improvement to a heuristic introduced by Chaitin for use in graph coloring register alloca-tion. Our modified heuristic produces better colorings, with less spill code. It has similar compile-time and implementation requirements. We present experimental data to compare the two methods ..."
Abstract
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Cited by 141 (8 self)
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We describe an improvement to a heuristic introduced by Chaitin for use in graph coloring register alloca-tion. Our modified heuristic produces better colorings, with less spill code. It has similar compile-time and implementation requirements. We present experimental data to compare the two
Optimal and Heuristic Global Code Motion for Minimal Spilling
"... Abstract. The interaction of register allocation and instruction scheduling is a well-studied problem: Certain ways of arranging instructions within basic blocks reduce overlaps of live ranges, leading to the insertion of less costly spill code. However, there is little previous research on the exte ..."
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overlaps. We evaluate solutions of this optimization problem using integer linear programming, where feasible, and a simple greedy heuristic. We conclude that global code motion with the sole goal of avoiding spills rarely leads to performance improvements because code is placed too conservatively
Spill code minimization techniques for optimizing compilers
, 1989
"... Global register allocation and spilling is commonly performed by solving a graph coloring problem. In this paper we present a new coherent set of heuristic methods for reducing the amount of spill code gen-erated. This results in more efficient (and shorter) compiled code. Our approach has been comp ..."
Abstract
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Cited by 75 (0 self)
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Global register allocation and spilling is commonly performed by solving a graph coloring problem. In this paper we present a new coherent set of heuristic methods for reducing the amount of spill code gen-erated. This results in more efficient (and shorter) compiled code. Our approach has been
A Polynomial Spilling . . . Allocation
, 2012
"... Register allocation is one of the most important, and one of the oldest compiler optimizations. Its purpose is to map temporary variables to either machine registers or main memory locations and explicit load/store instructions. The latter option is referred to as spilling. This paper addresses the ..."
Abstract
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the minimization of the spill code overhead, one of the di cult problems in register allocation. We devised a heuristic approach called layered. It is rooted in the recent advances in SSA-based register allocation. As opposed to the conventional incremental spilling approaches, our method incrementally allocates
Register Allocation via Graph Coloring
, 1992
"... Chaitin and his colleagues at IBM in Yorktown Heights built the first global register allocator based on graph coloring. This thesis describes a series of improvements and extensions to the Yorktown allocator. There are four primary results: Optimistic coloring Chaitin's coloring heuristic pes ..."
Abstract
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Cited by 155 (4 self)
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heuristic is emphasized when trying to color register pairs. My heuristic handles pairs as a natural consequence of its optimism. Rematerialization Chaitin et al. introduced the idea of rematerialization to avoid the expense of spilling and reloading certain simple values. By propagating rematerialization
Iterated Register Coalescing
- ACM Transactions on Programming Languages and Systems
, 1996
"... An important function of any register allocator is to target registers so as to eliminate copy instructions. Graph-coloring register allocation is an elegant approach to this problem. If the source and destination of a move instruction do not interfere, then their nodes can be coalesced in the inter ..."
Abstract
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Cited by 158 (4 self)
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in the interference graph. Chaitin's coalescing heuristic could make a graph uncolorable (i.e., introduce spills); Briggs et al. demonstrated a conservative coalescing heuristic that preserves colorability. But Briggs's algorithm is too conservative, and leaves too many move instructions in our programs. We
Reducing the Impact of Spill Code 2
, 1998
"... All graph-coloring register allocators rely on heuristics to arrive at a “good ” answer to the NP-complete problem of register allocation, resulting in suboptimal code due to spill code. We look at a post-pass to the allocator that removes unnecessary spill code by finding places where the availabil ..."
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All graph-coloring register allocators rely on heuristics to arrive at a “good ” answer to the NP-complete problem of register allocation, resulting in suboptimal code due to spill code. We look at a post-pass to the allocator that removes unnecessary spill code by finding places where
Improved Spill Code Generation for Software Pipelined Loops
, 1999
"... Software pipelining is a loop scheduling technique that extracts parallelism out of loops by overlapping the execution of several consecutive iterations. Due to the overlapping of iterations, schedules impose high register requirements during their execution. A schedule is valid if it requires at mo ..."
Abstract
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Cited by 16 (5 self)
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at most the number of registers available in the target architecture. If not, its register requirements have to be reduced either by decreasing the iteration overlapping or by spilling registers to memory. In this paper we describe a set of heuristics to increase the quality of register
Results 1 - 10
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91
