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Table 3. The same holds for the coolest applications in our suite (ammp for SpecFP and vpr for SpecInt).
2004
"... In PAGE 6: ...79 29.66 Table3 . Average IPC and power consumption for the 180nm base processor for our workload.... In PAGE 6: ... The sampled traces have been validated with the original full traces for accuracy and correct repre- sentation [9]. Table3 summarizes the benchmarks studied, including the IPC and average power (dynamic + leakage) consumption. As can be seen, for our processor, SpecInt has a higher average IPC and marginally higher power con- sumption than SpecFP.... ..."
Cited by 23
Table 3. The same holds for the coolest applications in our suite (ammp for SpecFP and vpr for SpecInt).
"... In PAGE 6: ...79 29.66 Table3 . Average IPC and power consumption for the 180nm base processor for our workload.... In PAGE 6: ... Sampling was used to limit the trace length to 100 million instructions per program. Table3 summarizes the benchmarks studied, including the IPC, and average power consumption. The power values include leakage power consumption.... ..."
Table 5: Benchmarks used. The set includes applica- tions from the SpecInt, SpecFP, and Mediabench bench- mark suites, as well as a few miscellaneous programs.
2003
"... In PAGE 7: ... 5.4 Experimental Results We use the familiar benchmarks in Table5 to test our sys- tem. All of the Trimaran certified benchmarks are included in the table4 [24].... In PAGE 7: ...4.2 General-Purpose Priority Functions We divided the benchmarks in Table5 into two sets6: a training set, and a test set. Instead of creating a priority 6We chose to train mostly on Mediabench applications because they compile and... ..."
Cited by 40
Table 5: Benchmarks used. The set includes applica- tions from the SpecInt, SpecFP, and Mediabench bench- mark suites, as well as a few miscellaneous programs.
2003
"... In PAGE 7: ... 5.4 Experimental Results We use the familiar benchmarks in Table5 to test our sys- tem. All of the Trimaran certi ed benchmarks are included in the table4 [24].... In PAGE 7: ...4.2 General-Purpose Priority Functions We divided the benchmarks in Table5 into two sets6: a training set, and a test set. Instead of creating a priority 6We chose to train mostly on Mediabench applications because they compile and... ..."
Cited by 40
Table 5: Benchmarks used. The set includes applica- tions from the SpecInt, SpecFP, and Mediabench bench- mark suites, as well as a few miscellaneous programs.
2003
"... In PAGE 7: ... 5.4 Experimental Results We use the familiar benchmarks in Table5 to test our sys- tem. All of the Trimaran certified benchmarks are included in the table4 [24].... In PAGE 7: ...4.2 General-Purpose Priority Functions We divided the benchmarks in Table5 into two sets6:a training set, and a test set. Instead of creating a priority 6We chose to train mostly on Mediabench applications because they compile and... ..."
Cited by 40
Table 5: Benchmarks used. The set includes applica- tions from the SpecInt, SpecFP, and Mediabench bench- mark suites, as well as a few miscellaneous programs.
"... In PAGE 7: ... 5.4 Experimental Results We use the familiar benchmarks in Table5 to test our sys- tem. All of the Trimaran certified benchmarks are included in the table4 [24].... In PAGE 7: ...4.2 General-Purpose Priority Functions We divided the benchmarks in Table5 into two sets6: a training set, and a test set. Instead of creating a priority 6We chose to train mostly on Mediabench applications because they compile and... ..."
Table 1 Four SPEC FP benchmarks
"... In PAGE 5: ... Using C pointer analysis, the compiler is able to identify the pointer aliases that actually occur in the program. This greatly increases the potential for parallelization As an example of what advanced compiler technology is capable of, Table1 shows the amount of loop-level parallelism extracted from four SPEC floating point benchmarks using the state of the art Stanford University intermediate format (SUIF) compiler system [1]. The percent- age of parallel coverage on each benchmark is the fraction of the sequential run time that is spent in the parallelized loops.... In PAGE 5: ... The percent- age of parallel coverage on each benchmark is the fraction of the sequential run time that is spent in the parallelized loops. The FORTRAN benchmarks require interprocedural analysis to get the high parallel coverage reported in Table1 . Without this analysis the parallel coverage on mdljdp2 drops to 13% and on ora the coverage drops to zero.... ..."
Cited by 1
Table 1 Four SPEC FP benchmarks
"... In PAGE 5: ... Using C pointer analysis, the compiler is able to identify the pointer aliases that actually occur in the program. This greatly increases the potential for parallelization As an example of what advanced compiler technology is capable of, Table1 shows the amount of loop-level parallelism extracted from four SPEC floating point benchmarks using the state of the art Stanford University intermediate format (SUIF) compiler system [1]. The percent- age of parallel coverage on each benchmark is the fraction of the sequential run time that is spent in the parallelized loops.... In PAGE 5: ... The percent- age of parallel coverage on each benchmark is the fraction of the sequential run time that is spent in the parallelized loops. The FORTRAN benchmarks require interprocedural analysis to get the high parallel coverage reported in Table1 . Without this analysis the parallel coverage on mdljdp2 drops to 13% and on ora the coverage drops to zero.... ..."
Cited by 1
Table 1: Instruction savings and speedup for the SPEC95fp benchmark suite and UTDSP kernels. Note that the current heuristics required compiler directives to seed the analysis for fpppp.
2000
"... In PAGE 9: ...3 Experimental Results 0% 10% 20% 30% 40% 50% 60% 70% 80% swim tomcatv mgrid su2cor hydro2d apsi wave5 applu turb3d fpppp fir lmsfir latnrm fft iir mult Percentage of Instructions Saved 64 bits 128 bits 256 bits Figure 8: Percentage of instructions eliminated with superword level parallelism. Table1 presents our results on a variety of datapath widths. Figures 8 and 9 present these numbers graphically in the form of instructions eliminated and speedup, respectively.... ..."
Cited by 59
Table 1: Instruction savings and speedup for the SPEC95fp benchmark suite and UTDSP kernels. Note that the current heuristics required compiler directives to seed the analysis for fpppp.
"... In PAGE 9: ...3 Experimental Results 0% 10% 20% 30% 40% 50% 60% 70% 80% swim tomcatv mgrid su2cor hydro2d apsi wave5 applu turb3d fpppp fir lmsfir latnrm fft iir mult Percentage of Instructions Saved 64 bits 128 bits 256 bits Figure 8: Percentage of instructions eliminated with superword level parallelism. Table1 presents our results on a variety of datapath widths. Figures 8 and 9 present these numbers graphically in the form of instructions eliminated and speedup, respectively.... ..."
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