aggressive cores and many hardware threads in the same chip. To address the need for chips delivering both high single-thread performance and many hardware threads, this thesis evaluates ScalableCoresinChipMultiprocessors:CMPsequippedwith cores that deliver high-performance (at high per-core power) when

depending on fluctuations of the workload, so to maximize productivity in an orthogonal manner with respect to traditional load balancing schemes, typically employed in the context of single-threaded simulation kernels. In order to optimize efficiency and reduce wait-for-lock-release phases while

Threading is a facility to allow multiple activities to coexist within a single process. Most modern operating systems support threads and the concept of threads has been around in various forms for many years. Java is the first mainstream programming language to explicitly include threading within

We have defined and implemented a kernel API that makes every exported operation fully interruptible and restartable, thereby appearing atomic to the user. To achieve interruptibility, all possible kernel states in which a thread may become blocked for a "long" time are represented

that uses such low-cost detectors to detect hardware faults, and a higher cost mechanism for diagnosis. However, all of the prior work in this context, including SWAT, assumes single-threaded applications and has not been demonstrated for multithreaded applications running on multicore systems. This paper

for acceleration while keeping one or two high-performance ILP cores on the die to guarantee single-thread performance. Although a major portion of the transistors are occupied by the acceleration cores, these resources will sit idle when running unparallelized legacy codes or the sequential part of an application

the effect of decreased reliability, a number of fault-tolerant architectures have been proposed that exploit the natural coarse-grained redundancy available in chip multiprocessors (CMPs). These architectures execute a single application using two threads, typically as one leading thread and one trailing

and quicker convergence for effective utilization of current multicore hardware. Speedup of about five over the sequential single-threaded implementation is achieved with both the schemes on a six-core machine. Convergence is also found in fewer number of generations. The methods described here-in can

Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow freely around data cache misses. As a result, they have difficulties overlapping independent misses with one another

is described as a separate object with a single-thread state diagram, which can be suspended and res...