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Multiscalar Processors

by Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar - In Proceedings of the 22nd Annual International Symposium on Computer Architecture , 1995
"... Multiscalar processors use a new, aggressive implementation paradigm for extracting large quantities of instruction level parallelism from ordinary high level language programs. A single program is divided into a collection of tasks by a combination of software and hardware. The tasks are distribute ..."
Abstract - Cited by 589 (30 self) - Add to MetaCart
are distributed to a number of parallel processing units which reside within a processor complex. Each of these units fetches and executes instructions belonging to its assigned task. The appearance of a single logical register file is maintained with a copy in each parallel processing unit. Register results

Multiple-banked register file architectures

by José-Lorenzo Cruz , Antonio González , Mateo Valero , Nigel P Topham - In International Symposium on Computer Architecture(ISCA-27 , 2000
"... Abstract The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor generations, as they are expected to increase the issue width (which implies more register ports) and the size of the ..."
Abstract - Cited by 146 (12 self) - Add to MetaCart
for processor performance (e.g. higher branch misprediction penalty) and complexity (more levels of bypass logic). To tackle these two problems, in this paper we propose a register file architecture composed of multiple banks. In particular we focus on a multi-level organization of the register file, which

Automatic Verification of Pipelined Microprocessor Control

by Jerry Burch, David Dill , 1994
"... We describe a technique for verifying the control logic of pipelined microprocessors. It handles more complicated designs, and requires less human intervention, than existing methods. The technique automaticMly compares a pipelined implementation to an architectural description. The CPU time nee ..."
Abstract - Cited by 290 (7 self) - Add to MetaCart
needed for verification is independent of the data path width, the register file size, and the number of ALU operations.

Self-Resetting CMOS Register File

by Wei Hwang, Senior Member, Rajiv V. Joshi, Senior Member, Walter H. Henkels
"... primary self-resetting CMOS (SRCMOS) circuit techniques. The register cell are completely level-sensitive scan design test com-patible. The fabricated register file occupies an area of 1.84 1.55 mm2, and the cell size is 21.6 30 m2. The high-performance register file is implemented in a multiblock ..."
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primary self-resetting CMOS (SRCMOS) circuit techniques. The register cell are completely level-sensitive scan design test com-patible. The fabricated register file occupies an area of 1.84 1.55 mm2, and the cell size is 21.6 30 m2. The high-performance register file is implemented in a

The Chimera Reconfigurable Functional Unit

by Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jeffrey P. Kao , 2004
"... By strictly separating reconfigurable logic from the host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper, we describe Chimaera, a system that overcomes the communication bottleneck by integrating reconfigurable logic into the host proce ..."
Abstract - Cited by 190 (19 self) - Add to MetaCart
processor itself. With direct access to the host processor’s register file, the system enables the creation of multi-operand instructions and a speculative execution model key to high-performance, general-purpose reconfigurable computing. Chimaera also supports multi-output functions and utilizes partial

The Multicluster Architecture: Reducing Cycle Time Through Partitioning

by Keith L. Farkas, Paul Chow, Norman P. Jouppi, Zvonko Vranesic , 1997
"... The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of the architecture are distributed across multiple clusters, and each cluster is assigned a subset of the architectural regis ..."
Abstract - Cited by 176 (0 self) - Add to MetaCart
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of the architecture are distributed across multiple clusters, and each cluster is assigned a subset of the architectural

A Scalable Register File Architecture for Dynamically Scheduled Processors

by Steven Wallace, Steven Wallace, Nader Bagherzadeh, Nader Bagherzadeh - In International Conference on Parallel Architectures and Compilation Techniques , 1996
"... A major obstacle in designing dynamically scheduled processors is the size and port requirement of the register file. By using a multiple banked register file and performing dynamic result renaming, a scalable register file architecture can be implemented without performance degradation. In addition ..."
Abstract - Cited by 70 (1 self) - Add to MetaCart
A major obstacle in designing dynamically scheduled processors is the size and port requirement of the register file. By using a multiple banked register file and performing dynamic result renaming, a scalable register file architecture can be implemented without performance degradation

The Anatomy of the Register File in a Multiscalar Processor

by Scott Breach Vijaykumar, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi - In Proceedings of the 27th Annual International Symposium on Microarchitecture , 1994
"... This paper presents the operation of the register file in the Multiscalar architecture. The register file provides the appearance of a logically centralized register file, yet is implemented as physically decentralized register files, queues, and control logic in a Multiscalar processor. We address ..."
Abstract - Cited by 36 (13 self) - Add to MetaCart
This paper presents the operation of the register file in the Multiscalar architecture. The register file provides the appearance of a logically centralized register file, yet is implemented as physically decentralized register files, queues, and control logic in a Multiscalar processor. We address

ABSTRACT Virtualizing Register Context by

by David W. Oehmke, Chair Trevor, N. Mudge, David W. Oehmke
"... A processor designer may wish for an implementation to support multiple reg-ister contexts for several reasons: to support multithreading, to reduce context switch overhead, or to reduce procedure call/return overhead by using register windows. Conventional designs require that each active context b ..."
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multiple context support and register file size by mapping registers to memory, thereby decoupling the logical register requirements of active contexts from the contents of the physical register file. Just as caches and virtual memory allow a processor to give the illusion of numerous multi

Banked Multiported Register Files for High-Frequency Superscalar Microprocessors

by Jessica H. Tseng, Krste Asanovic - In International Symposium on Computer Architecture , 2003
"... Multiported register files are a critical component of high-performance superscalar microprocessors. Conventional multiported structures can consume significant power and die area. We examine the designs of banked multiported register files that employ multiple interleaved banks of fewer ported regi ..."
Abstract - Cited by 64 (5 self) - Add to MetaCart
simpler and faster control logic while only slightly increasing the number of ports per bank. We present area, delay, and energy numbers extracted from layouts of the banked register file. For a four-issue superscalar processor, we show that we can reduce area by a factor of three, access time by 20
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