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The Case for a Single-Chip Multiprocessor

by Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, Kunyung Chang - IEEE Computer , 1996
"... Advances in IC processing allow for more microprocessor design options. The increasing gate density and cost of wires in advanced integrated circuit technologies require that we look for new ways to use their capabilities effectively. This paper shows that in advanced technologies it is possible to ..."
Abstract - Cited by 440 (6 self) - Add to MetaCart
to implement a single-chip multiproces-sor in the same area as a wide issue superscalar processor. We find that for applications with little parallelism the performance of the two microarchitectures is comparable. For applications with large amounts of parallelism at both the fine and coarse grained levels

Migration in Single Chip Multiprocessors

by Kelly A. Shaw, William J. Dally - Computer Architecture Letters , 2002
"... Abstract — Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads bas ..."
Abstract - Cited by 11 (0 self) - Add to MetaCart
Abstract — Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads

Migration in Single Chip Multiprocessors

by unknown authors
"... Abstract — Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads bas ..."
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Abstract — Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads

Migration in Single Chip Multiprocessors

by Kelly Shaw And, Kelly A. Shaw, William J. Dally - Computer Architecture Letters , 2002
"... Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads based on vecto ..."
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Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads based

SINGLE-CHIP CMOS ANEMOMETER

by E Mayer, A. Haberli, H. Jacobs, G. Ofner, H. Baltes
"... For the first time a packaged single-chip anemometry microsystem is reported. The system includes a thermal CMOS flow sensor with on-chip power management, signal conditioning, and A/D conversion. It is fabricated using an industrial IC process followed by post-CMOS micromachining. The system is pac ..."
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For the first time a packaged single-chip anemometry microsystem is reported. The system includes a thermal CMOS flow sensor with on-chip power management, signal conditioning, and A/D conversion. It is fabricated using an industrial IC process followed by post-CMOS micromachining. The system

Simultaneous Multithreading: Maximizing On-Chip Parallelism

by Dean M. Tullsen , Susan J. Eggers, Henry M. Levy , 1995
"... This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar’s multiple functional units in a single cycle. We present several models of simultaneous multithreading and compare them with alternative organizations: a wide s ..."
Abstract - Cited by 823 (48 self) - Add to MetaCart
superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing architectures. Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor. Simultaneous

Piranha: A scalable architecture based on single-chip multiprocessing

by Luiz André Barroso, Kourosh Gharachorloo, Robert Mcnamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese - SIGARCH Comput. Archit. News , 2000
"... The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instructionlevel parallelism. Meanwhile, such designs are especially ill suited for important commercial application ..."
Abstract - Cited by 244 (7 self) - Add to MetaCart
alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors

A Single-Chip Multiprocessor

by unknown authors , 1997
"... ntegrated circuit processing technology offers increasing integration density, which fuels micro-processor performance growth. Within 10 years it will be possible to integrate a billion transistors on a reasonably sized silicon chip. At this integration level, it is necessary to find parallelism to ..."
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ntegrated circuit processing technology offers increasing integration density, which fuels micro-processor performance growth. Within 10 years it will be possible to integrate a billion transistors on a reasonably sized silicon chip. At this integration level, it is necessary to find parallelism

Introduction to Single Chip

by Microwave Plls
"... Synthesizer and Phase Locked Loop (PLL) figures of merit including phase noise � spurious output and lock time � at microwave ..."
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Synthesizer and Phase Locked Loop (PLL) figures of merit including phase noise � spurious output and lock time � at microwave

Single Chip Realizes

by Direct-conversion Rx
"... nent count, along with the elimination of expensive fil-tering has made direct con-version very appealing as an architecture for transmit and receive functions. However, it is only recently that components which facilitate its practical implementation have become available. Although the direct-conve ..."
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nent count, along with the elimination of expensive fil-tering has made direct con-version very appealing as an architecture for transmit and receive functions. However, it is only recently that components which facilitate its practical implementation have become available. Although the direct-conversion approach reduces the component count, it also adds design challenges. In the super-heterodyne approach (Fig. 1, left), by driving the mixer with a frequency-agile LO, the frequency of the desired signal or channel (which is generally varies in a multi-user system) is converted to a fixed frequency. Once the desired signal has been converted to a fixed IF, it can be processed by highly selective narrowband filtering using a surface-acoustic-wave (SAW) filter. In addi-tion, all subsequent frequency transla-tions can be effected using fixed-frequency LOs. The other important function per-formed at IF in a superheterodyne sys-tem is signal amplification. Fixed-gain amplification, in the form of low-noise amplifiers (LNAs), is generally applied at RF, while signal leveling is general-
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