to implement a single-chip multiproces-sor in the same area as a wide issue superscalar processor. We find that for applications with little parallelism the performance of the two microarchitectures is comparable. For applications with large amounts of parallelism at both the fine and coarse grained levels

Abstract — Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads

Abstract — Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads

Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to take advantage of these new costs. We present a technique which simultaneously migrates data and threads based

For the first time a packaged single-chip anemometry microsystem is reported. The system includes a thermal CMOS flow sensor with on-chip power management, signal conditioning, and A/D conversion. It is fabricated using an industrial IC process followed by post-CMOS micromachining. The system

superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing architectures. Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor. Simultaneous

alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors

ntegrated circuit processing technology offers increasing integration density, which fuels micro-processor performance growth. Within 10 years it will be possible to integrate a billion transistors on a reasonably sized silicon chip. At this integration level, it is necessary to find parallelism

Synthesizer and Phase Locked Loop (PLL) figures of merit including phase noise � spurious output and lock time � at microwave

nent count, along with the elimination of expensive fil-tering has made direct con-version very appealing as an architecture for transmit and receive functions. However, it is only recently that components which facilitate its practical implementation have become available. Although the direct-conversion approach reduces the component count, it also adds design challenges. In the super-heterodyne approach (Fig. 1, left), by driving the mixer with a frequency-agile LO, the frequency of the desired signal or channel (which is generally varies in a multi-user system) is converted to a fixed frequency. Once the desired signal has been converted to a fixed IF, it can be processed by highly selective narrowband filtering using a surface-acoustic-wave (SAW) filter. In addi-tion, all subsequent frequency transla-tions can be effected using fixed-frequency LOs. The other important function per-formed at IF in a superheterodyne sys-tem is signal amplification. Fixed-gain amplification, in the form of low-noise amplifiers (LNAs), is generally applied at RF, while signal leveling is general-