### Table 2: Quality values using the simple chaining method.

in Abstract

"... In PAGE 6: ...n Fig. 4. In this simpler chaining procedure a C8C7CB is gen- erated using a trivial heuristic, without consideration of the flexibility of the result. Table2 shows the results obtained using this chaining version. We can see that the solution quality degrades greatly compared to the original algorithm.... ..."

### Table 1 Communication Operations Required for a Simple Chain of Processors

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### Table 1 Communication Operations Required for a Simple Chain of Processors

### Table 2: Data redistribution costs of the six data partitioning schemes. 4.1 A simple task chain

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"... In PAGE 9: ... In [17] we studied and tabulated the cost functions of data redistribution from one partition to another. The cost table is reproduced in Table2 . Note that the communication algorithms used to generate Table 2 may not be optimal and other algorithms for all-to-all communication could be used, e.... In PAGE 24: ... Edges incident on the starting and the end nodes were of zero weight. Costs of all other edges were tabulated in Table2 . The... ..."

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### Table XIV Accuracy for chains with odd number of cysteines after a simple ranking mechanism is applied for the SVM prediction

### Table 3: A Chaining KB

"... In PAGE 12: ...5 A Chaining Example We now extend the simple example introduced in Section 2.3 with additional chaining rules as shown in Table3 . The training case is also adapted to utilise these additional rules: we want a recommendation for someone who likes a French-style, red wine to drink with chicken in a red wine sauce for $3.... ..."

### Table 3. A chain for M12

"... In PAGE 34: ... In Table 2 we present another subset chain for M11 to demonstrate a new idea, namely that information gained during an IsMember test can be used further. Table3 contains a subset chain for the sporadic simple Mathieu group M12. In Table 4 we describe a subset chain for the sporadic simple Mathieu group M22.... ..."

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### Table 4: Vector operations in the STREAM benchmark. Copy measures transfer rates in the absence of arithmetic; Scale adds a simple multiply; Sum adds a third operand; Triad allows for chained vector operations.

"... In PAGE 5: ...4.3 Memory Bandwidth and Latency Benchmarks STREAM is a synthetic benchmark that measures the sus- tainable memory bandwidth of a processor system using four long vector operations, described in Table4 [21]. The array sizes used by the benchmark are defined to be larger than the cache of the machine being tested, and data is not reused.... ..."

### Table 9. A chain for Ly

"... In PAGE 34: ... We conclude this section with a larger example, in which we demonstrate yet another idea, namely that there may be branches in chains, leading to different behaviour of the algorithm under certain circumstances, that may occur during the calculation. See Table9 for details and Note (i) to Table 9 for an explanation. We have implemented the generalised sifting algorithms using the subset chains de- scribed in the tables below for some of the sporadic simple groups.... ..."

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### Table 2: A comparison of the delays of different structures for (a) a 32-bit carry, and (b) a non-carry computation of a function, f(X,Y,Z). The results of the simple delay model described earlier suggest that the Brent-Kung carry chain has the best performance of any of the carry chains. However, the performance results used to make this decision are based only on the simple delay model, which may not accurately reflect the true delays. The simple delay model does not take into account transistor sizes or routing delays. Therefore, in order to get more accurate comparisons the carry chains were sized using Logical Effort [Sutherland90], layouts were created, and timing numbers were obtained from Spice for a 0.6 micron process. Only the most promising carry chains were chosen for implementation. These include the simple Ripple Carry, which can be found in current FPGAs, as well as the new Optimized Ripple and Brent-Kung carry chains. Additionally, Dual Rail Brent-Kung and Dual Rail Optimized Ripple carry chains were also implemented in VLSI to determine whether the dual rail optimization can increase performance. Diagrams showing the VLSI layouts can be found in Appendix C.

"... In PAGE 22: ... Table2 shows the delays of a 32-bit carry for the carry chains that were implemented. Notice that the delay for simple Ripple Carry chain is 23.... In PAGE 22: ... Appendix D contains timing numbers for variable length carries of the various carry chains. Table2 also shows the delays of the FPGA cell assuming that the cell is programmed to compute a function of 3 variables and avoid the carry chain (as shown by Mux 5 in Figure 4c). The delay for the simple Ripple Carry chain in this case is 1.... ..."