### Table 1: Minimizing Power under Delay Constraints

1995

"... In PAGE 3: ... Results on several benchmarks are presented. Table1 illustrates the power-delay tradeo#0B for various circuits under various delay speci#0Ccations. The #0Crst column lists the circuit name; the circuits have been chosen from the LgSynth91 benchmarks.... ..."

Cited by 1

### Table 4. Experimental results on optimal test access architecture design under power constraints: (a) S1 (b) S2.

2000

"... In PAGE 5: ... Gi can be obtained from power models for core i. Experimental results for power-constrained test access archi- tecture design for S1 and S2 are shown in Table4 . For our ex- periments, we approximated Gi by the number of gates in core i.... In PAGE 5: ... On the other hand, for higher values of W, the testing time is affected substantially. For example, in Table4 (a), for W 24 and power budget of 300 units, the testing time does not decrease with an increase in W due to power constraints. In some cases, the ILP problem may even be infeasible for higher test widths, e.... In PAGE 5: ...g. in Table4 (b) with W = 48 and power budget of 300 units for S2. Comparing with Table 2, we note that the width distribution is also significantly different due to power constraints.... In PAGE 5: ... This is achieved using a width distribution of (10,10) and test bus assignment (2,2,2,2,2,2,2,2,2,1). However, as seen from Table4 . for test width W = 24, the test bus assignment has to be changed to meet power constraints, and the minimum testing time increases to 471900 cycles.... ..."

Cited by 44

### Table 4. Experimental results on optimal test access architecture design under power constraints: (a) S 1 (b) S 2 .

"... In PAGE 5: ... G i can be obtained from power models for core i. Experimental results for power-constrained test access archi- tecture design for S 1 and S 2 are shown in Table4 . For our ex- periments, we approximated G i by the number of gates in core i.... In PAGE 5: ... On the other hand, for higher values of W, the testing time is affected substantially. For example, in Table4 (a), for W 24 and power budget of 300 units, the testing time does not decrease with an increase in W due to power constraints. In some cases, the ILP problem may even be infeasible for higher test widths, e.... In PAGE 5: ...g. in Table4 (b) with W =48 and power budget of 300 units for S 2 . Comparing with Table 2, we note that the width distribution is also significantly different due to power constraints.... In PAGE 5: ... This is achieved using a width distribution of (10,10) and test bus assignment (2,2,2,2,2,2,2,2,2,1). However, as seen from Table4 . for test width W =24, the test bus assignment has to be changed to meet power constraints, and the minimum testing time increases to 471900 cycles.... ..."

### Table 2: Comparing count-sort with the MasPar library sort psort8u counting clockticks.

1995

"... In PAGE 9: ... The second was timed against vbsort which is discussed in [8]. In Table2 , wegive timings in number of clockticks to sort 8-bit integers on 8192 proces- sors. Inputs were distributed across the mesh using the pseudo-random number generator p random.... ..."

Cited by 1

### Table 2: Comparing count-sort with the MasPar library sort psort8u counting clock ticks.

"... In PAGE 9: ... The second was timed against vbsort which is discussed in [8]. In Table2 , we give timings in number of clock ticks to sort 8-bit integers on 8192 proces- sors. Inputs were distributed across the mesh using the pseudo-random number generator p random.... ..."

### Table 1. Characteristics of constraints for several algorithms

2004

"... In PAGE 11: ... Thus the complexity of the constraints we gathered was mostly relatively small and hence manageable in a short amount of time. In particular our tool is able to generate the complete sets of test cases regarding the def-use chain coverage for the algorithms mentioned in Table1 in a few seconds. This table shows what kinds of constraints occur in the example applications we have considered.... ..."

Cited by 3

### Table 1: Results for various power and delay constraints

"... In PAGE 4: ... Both of these parameters are normalized with respect to the parameter values when all transistors in the macrocells are min-sized. The notation used here is that the factor under the D spec #28P#29 column in Table1 divides #28multiplies#29 the delay#28power dissipation#29 of a min-sized inverter. For example, a 4x factor for delay implies a de- lay that is a quarter of that for the min-sized cell, and a 10x factor for power implies that the power dissipation is 10 times that for the min-sized cell.... In PAGE 4: ... Results of the algorithm on four di#0Berent gates are shown here: INV, NAND2, NOR3, and 2,2-AOI, for dif- ferentvalues of D spec . Table1 shows the height h and width w of each cell, the number of SPICE simulations, the number of iterations of the convex programming algo- rithm, and the CPU time on an HP715 workstation. Table 1: Results for various power and delay constraints... In PAGE 4: ...Since our method solves the underlying convex pro- gramming problem exactly, the power dissipation shown in Table1 correspond to the globally optimum solution to the problem for that layout style, with an accuracy that is dictated by the user-speci#0Ced termination criterion #5B7#5D. It was observed from our experiments that, as expected, as D spec is made more stringent, the area and the power dissipation of the #0Dexible macrocell increase.... ..."

### Table 1: Minimizing Power under Delay Constraints

"... In PAGE 21: ... 6 Experimental Results The algorithm described above has been implemented as a C program on an HP735 workstation. Table1 illustrates the power-delay tradeo#0B for various benchmark circuits under various delay speci#0Ccations. The #0Crst column lists the circuit name.... ..."

### Table 2: Power plantvalue vs. physical constraints

"... In PAGE 7: ... The case with units on at all hours is consid- ered to be a good measurement of the limiting case for increasing t on , which corresponds to the lowest mean pro#0Ct, and the highest variance among all test cases. The last column of Table2 corresponds to value ob- tained without considering decision lead time. This also represents the value obtained by the approach us- ing #0Cnancial option theory presented in Section 3.... ..."

### Table 1: Location of Constraint Enforcement Constraint Enforcement Real/reactive bus power balance Power flow

"... In PAGE 3: ... Practically all the constraints of (1) are considered by either enforcing them using the power flow, or, in the case of most nonbonding inequality constraints, monitoring but not enforcing them as long as they remain nonbonding. Table1 summarizes the enforcement of the various constraints. Table 1: Location of Constraint Enforcement Constraint Enforcement Real/reactive bus power balance Power flow ... ..."