### Table 2 lists the E85 laboratory assignments. These laboratories are completed using Xilinx ISE 6.3i with ModelSim 6.0 for simulation and Synplify Pro 8.1 for synthesis. In the first three labs, the students use schematic entry to understand basic logic circuits. They use combinational logic gates in the first two labs followed by sequential logic circuits in the third lab. They follow the steps of (1) describing the problem, (2) writing truth tables, (3) deriving the Boolean equations, and (4) translating the equations to hardware. In the fourth and fifth labs students transition to a hardware description language (HDL). In our class, we use Verilog, but

### Table 1: Fault Injection on sequential circuits A more detailed study of the performance gain that stems from the adoption of the FPGA- based Fault Injection for analyzing sequential custom logic is reported in [15], where figures are reported showing how the speed-up increases with the number of simulated vectors.

"... In PAGE 8: ... The simulator concurrently simulates 32 faulty circuits and stops the simulation of a fault as soon as the fault effects reach the circuit outputs. The last two columns of Table1 report the results we attained by running this tool on a Sun UltraSparc running at 300 MHz and equipped with 256 MB of RAM, as well as the speed-up attained with our FPGA-based system. The results of Table 1 show that the FPGA-based environment attains speed-up factors ranging from 26 to 30, pointing out that the effectiveness of the approach generally increases ... In PAGE 8: ... The last two columns of Table 1 report the results we attained by running this tool on a Sun UltraSparc running at 300 MHz and equipped with 256 MB of RAM, as well as the speed-up attained with our FPGA-based system. The results of Table1 show that the FPGA-based environment attains speed-up factors ranging from 26 to 30, pointing out that the effectiveness of the approach generally increases ... ..."

### Table 6: Comparison to Precomputation for Traditional Sequential Circuits. tions with extended support (including some of the circuit outputs). The compactness and expressive power of ADDs allow us to accurately compute the probability of the activation function, and to de- velop algorithms that control the optimization of the global power dissipation with superior accuracy, compared to previous approaches. Our optimization strategy also relies on an integrated synthesis methodology that aims at reducing the overhead of the redundant clock-gating logic by e ectively exploiting the additional don apos;t care conditions in the combinational logic. The results are promising, since we obtain power reductions as high as 34% with negligible area and performance degradations.

1997

"... In PAGE 24: ... We have thus implemented the various extensions within our framework, and we have compared the results to those obtained by adding to the original circuit the clock-gating logic. The data in Table6 shows the ine ectiveness of the precomputation-based approach for this type of designs (savings, in percentage, are computed with respect to the reference circuits). The reason for this poor behavior lies in that the precomputation function never attempts to stop the present-state inputs, which represent the majority of the inputs to the combinational logic for sequential circuits with a realistic number of memory elements.... ..."

Cited by 12

### Table 2n3a Sequential Benchmark Circuits

"... In PAGE 4: ... For the sake of simplicityn2c the circuits were mapped using a cell library of simple logic gates so that the controlling values of the combinational elen2d ments can be determined easily. The experimental results are presented in Table 1 and Table2 n2c in which the number of inputs n28In29n2c outputs n28On29n2c and registers n28Rn29 of the circuits are listed. The number of literalsn2c levelsn2c and average power consumption are shown for both the original circuit and the circuit with desensin2d tization.... In PAGE 4: ... For examplen2c in the case of muxn2cwe atn2d tained a 34n25 power reduction without increasing the number of literals or levels. Table2 presents the results for sequential benchn2d mark circuits. Some of the registers were replicated to maximize the reduction in switching activity.... ..."

### Table 3: Performance comparison of the partitioning procedure.

in A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area

1993

"... In PAGE 3: ...eriod without clockskew optimization is about 32.5. On the other hand, using clockskew optimization, the mini- mum period can be as small as 22, which gives an almost 33#25 improvement in terms of clock speed. Table3 gives the experimental results for the partition- ing procedure. Since most of the ISCAS89 circuits consist of only one combinational block, we generated some syn- chronous sequential random logic circuits.... In PAGE 3: ... Since most of the ISCAS89 circuits consist of only one combinational block, we generated some syn- chronous sequential random logic circuits. The number of gates and FF apos;s in those circuits are shown in Table3 . For each circuit, we conduct three experiments.... ..."

Cited by 1

### Table 1: Circuits from the MCNC benchmarks used to eval-

1998

"... In PAGE 5: ...6 Experiments To show that precomputation is a viable option in sequential logic resynthesis, we implemented our heuristic and com- pared resynthesis that employs precomputation with one that does not. Our set of circuits, summarized in Table1 , was selected from the MCNC sequential multilevel circuits. We used only a subset of the 40 circuits, eliminating large circuits that demanded large memory or long CPU time in SIS #5B11#5D, a logic optimization program we used to resynthesize, map, and retime the circuits.... ..."

Cited by 2

### Table 2: Sequent rules corresponding to circuit links

"... In PAGE 6: ... In valid (or sequential) nets C will havetobevalid as well;; this will be checked using the sequentialization process of Appendix B, or, equivalently,by showing that the circuit can be built inductively. Since some of these connectives will not be familiar (and because we use a di erent notation from just about anyone else!|Lambek uses n ;;=for ; ;; ;,and : ; ;; ; : for 5;; 4), the sequent rules that correspond to these links are given in Table2 . In commutative logics the reader can add the exchange rule for himself.... In PAGE 12: ...n the noncommutative logic. In Appendix B we presentavalid sequentialization process. An example of a planar non-sequential circuit which satis es the net criterion is given in Figure 16. The sequent rules given in Table2 are all valid in the noncommutative logics;; for the commutative logics, where the circuits need not be planar, one must add the exchange rules in the obvious way. In Figure 3 are some (valid) circuits.... In PAGE 15: ... Logical theories and categorical doctrines We shall deal with several logical theories (and the corresponding categorical structures) in this paper. The full system using all the binary connectives ;; ;; ; ;; ;;; 4;; 5 and the constants gt;;; ? and using the sequent rules of Table2 (or equivalently the circuit links of Table 1) is Lambek apos;s bilinear logic BILL.We also consider the fragment of bilinear logic which omits the connectives 4;; 5;;we call this noncommutative logic GILL.... In PAGE 15: ....1. Remark. (Cut elimination and FILL) Neither the commutative nor noncommuta- tiveversions of FILL, if presented as a sequent calculus (as in Table2 , with the restriction of Remark 1.1) satis es cut elimination.... In PAGE 18: ...102 in Table2 ) corresponds categorically to having an inverse (costrength) to this family of maps: A ; (B C) ;! (A ; B) C.Wecancheck that in the category of circuits with the more general \boxed quot; links we do indeed havesuch an isomorphism;; half of this exercise is illustrated in Figure 4.... ..."

### Table 2: Sequential Circuit Results

1994

Cited by 58

### Table 1. Benchmark circuit delay information.

"... In PAGE 4: ... The method we use to place the spares is described in [5]. The results presented in Table1 are based on implementing the seven benchmarks using the ORCA2C15 FPGA. Two of the benchmark circuits we implemented were from the DARPA ACS program.... In PAGE 4: ... We relied on the the ORCA Foundry Trace tool to calculate the worst-case propagation delay through the combinational logic for each circuit. Table1 shows the worst-case delay for the critical paths in the seven circuits we implemented. Column Type indicates the type of the circuit - S for sequential and C for combinational.... ..."

### Table 2. Comparison of sequential circuit test generation tools circuit faults HITEC4 GATEST5 DECIDER6 current approach

2005

"... In PAGE 11: ....4.3. Experimental results In Table2 , comparison of test generation results of four ATPG tools are presented on six hierarchical benchmarks. The other tools considered in the comparative experiments include HITEC4, which is a logic-level deterministic ATPG, GATEST5 as a genetic-algorithm based tool and a hierarchical ATPG DECIDER6.... In PAGE 12: ... The test generation times for the proposed method include both, test generation time and evaluation of the gate-level stuck-at fault coverage by the fault simulator. In Table2 , fault coverages and run times in seconds for each example circuit are presented. The average fault coverage achieved by each tool is reported in the last row.... ..."