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Design Diversity For Concurrent Error Detection In Sequential Logic Circuits
 IN SEQUENTIAL LOGIC CIRCUITS,” VLSI TEST SYMP
, 2001
"... We present a technique using diverse duplication to implement concurrent error detection (CED) in sequential logic circuits. We examine three different approaches for this purpose: (1) Identical state encoding of the two sequential logic implementations, duplication of flipflops, diverse implementa ..."
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Cited by 2 (2 self)
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We present a technique using diverse duplication to implement concurrent error detection (CED) in sequential logic circuits. We examine three different approaches for this purpose: (1) Identical state encoding of the two sequential logic implementations, duplication of flipflops, diverse
A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits
 ACM/IEEE 31st Design Automation Conference
, 1994
"... We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a nonlinear system of equations of size N , where the variables correspond to state line probabilities. We show that the approximation method is within 3% o ..."
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Cited by 39 (1 self)
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We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a nonlinear system of equations of size N , where the variables correspond to state line probabilities. We show that the approximation method is within 3
Using Evolutionary Strategies Algorithm in the Evolutionary Design of Sequential Logic Circuits
"... Evolvable hardware (EHW) is a set of techniques that are based on the idea of combining reconfiguration hardware systems with evolutionary algorithms. In other word, EHW has two sections; the reconfigurable hardware and evolutionary algorithm where the configurations are under the control of an evol ..."
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of an evolutionary algorithm. This paper, suggests a method to design and optimize the synchronous sequential circuits. Evolutionary Strategies algorithm (ES) was applied as evolutionary algorithm. In this approach, for building input combinational logic circuit of each DFF, and also output combinational logic
Waiting False Path Analysis of Sequential Logic Circuits for Performance Optimization
 In Proceedings of the International Conference on ComputerAided Design
, 1998
"... This paper introduces a new class of false path, which is sensitizable but does not affect the decision of the clock period. We call such false paths waiting false paths, which correspond to multicycle operations controlled by wait states. The allowable delay time of waiting false paths is greater ..."
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Cited by 7 (2 self)
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of FSM. We have applied our method to 30 ISCAS89 FSM benchmarks and found that 22 circuits include such paths. 11 circuits among them include such paths which are critical paths, where the delay is measured as the number of gates on the path. Informations on such paths can be used in the logic synthesis
Performance and reliability driven clock scheduling of sequential logic circuits
 in ASPDAC
, 1997
"... Abstract  It is known that the clockperiod in a sequential circuit can be shorter than the maximum signal delay between registers if the clock arrival time to each register is controlled. We propose an algorithm to nd the minimum clockperiod of a circuit whose signal propagation delays are given ..."
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Cited by 5 (3 self)
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Abstract  It is known that the clockperiod in a sequential circuit can be shorter than the maximum signal delay between registers if the clock arrival time to each register is controlled. We propose an algorithm to nd the minimum clockperiod of a circuit whose signal propagation delays
SingleFault FaultCollapsing Analysis in Sequential Logic Circuits
, 2016
"... All intext references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately. ..."
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All intext references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately.
A ComputerAided Design Methodology for Low Power Sequential Logic Circuits
, 1996
"... Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat dissipation as well as battery life. For some systems, power ..."
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Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat dissipation as well as battery life. For some systems, power has become the most critical design constraint. In this
A ComputerAided Design Methodology for Low Power Sequential Logic Circuits by
, 1996
"... C airman, Deprtment Committee on. Graduate Students ..."
Techniques for the Power Estimation of Sequential Logic Circuits Under UserSpecified Input Sequences and Programs
 IEEE Transactions on VLSI Systems
, 1994
"... We describe an approach to estimate the average power dissipation in sequential logic circuits under userspecified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or proc ..."
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Cited by 38 (9 self)
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We describe an approach to estimate the average power dissipation in sequential logic circuits under userspecified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller
Evolutionary algorithms and theirs use in the design of sequential logic circuits. Genetic Programming and Evolvable Machines
 Genetic Programming and Evolvable Machines
, 2004
"... Abstract. In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use of genetic algorithms (GA) for the state ..."
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Cited by 3 (1 self)
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Abstract. In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed method consists of four main stages. The first stage is concerned with the use of genetic algorithms (GA
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