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SIS: A System for Sequential Circuit Synthesis
, 1992
"... SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential inputoutput b ..."
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Cited by 527 (44 self)
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SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logiclevel description of a sequential circuit, it produces an optimized netlist in the target technology while preserving the sequential input
Sequential Circuits
"... � Digital circuits are considered [1] as � Combinational: the outputs at any instant of time are entirely dependent upon the inputs present at that time. � Sequential: the outputs at any instant of time are entirely dependent upon the inputs and state of the circuit present at that time. Sequential ..."
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� Digital circuits are considered [1] as � Combinational: the outputs at any instant of time are entirely dependent upon the inputs present at that time. � Sequential: the outputs at any instant of time are entirely dependent upon the inputs and state of the circuit present at that time. Sequential
Robustness of Sequential Circuits
"... Abstract—Digital components play a central role in the design of complex embedded systems. These components are interconnected with other, possibly analog, devices and the physical environment. This environment cannot be entirely captured and can provide inaccurate input data to the component. It is ..."
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Cited by 6 (2 self)
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. It is thus important for digital components to have a robust behavior, i.e. the presence of a small change in the input sequences should not result in a drastic change in the output sequences. In this paper, we study a notion of robustness for sequential circuits. However, since sequential circuits may have
Automatic verification of sequential circuits using temporal logic
 Dubois ACM Computing Surveys
, 1997
"... Automatic verification of sequential circuits using temporal logic ..."
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Cited by 84 (13 self)
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Automatic verification of sequential circuits using temporal logic
Power Estimation in Sequential Circuits
, 1995
"... A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole ..."
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Cited by 30 (6 self)
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A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole
Sequential Circuits for Relational Analysis
"... The Alloy toolset has been gaining popularity as an alternative to traditional manual testing and checking for design correctness. Alloy uses a firstorder relational logic for modeling designs. The Alloy Analyzer translates Alloy formulas for a given scope, i.e., a bound on the universe of discour ..."
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Cited by 5 (5 self)
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of discourse, to Boolean formulas in conjunctive normal form (CNF), which are subsequently checked using propositional satisfiability solvers. We present SERA, a novel algorithm that compiles a relational logic formula for a given scope to a sequential circuit. There are two key advantages of sequential
Symbolic model checking for sequential circuit verification
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 1994
"... The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDD’s) [7] and partitioned trunsirion relations [lo], 1111. Because this representation captures some of the regularity in the state space of circuit ..."
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Cited by 271 (12 self)
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of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5 x 10^120 states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we
Retiming Sequential Circuits for Low Power
 In Proceedings of the Int'l Conference on ComputerAided Design
, 1993
"... Switching activity is the primary cause of power dissipation in CMOS combinational and sequential circuits. We give a method of estimating power in pipelined sequential CMOS circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit. We expl ..."
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Cited by 84 (9 self)
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Switching activity is the primary cause of power dissipation in CMOS combinational and sequential circuits. We give a method of estimating power in pipelined sequential CMOS circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit. We
Sequential Circuits ∗ Kazuhiro Nakamura
, 2001
"... The timing analysis andoptimization of sequential circuits become more and more important with the advances of VLSI technologies. We should cope with the clock frequency more than 2 GHz near the future. The clock frequencies of sequential circuits are decided based on the maximum delay time of paths ..."
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The timing analysis andoptimization of sequential circuits become more and more important with the advances of VLSI technologies. We should cope with the clock frequency more than 2 GHz near the future. The clock frequencies of sequential circuits are decided based on the maximum delay time
Design Replacements for Sequential Circuits
, 1996
"... In this dissertation we study the problem of design replacements for synchronous sequential circuits. There have been previous efforts to characterize the criterion for replacement for such circuits. However, all previous attempts either make implicit or explicit assumptions about the design or the ..."
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Cited by 11 (4 self)
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In this dissertation we study the problem of design replacements for synchronous sequential circuits. There have been previous efforts to characterize the criterion for replacement for such circuits. However, all previous attempts either make implicit or explicit assumptions about the design
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