This paper presents a novel disk storage architecture called DCD, Disk Caching Disk, for the purpose of optimizing I/O performance. The main idea of the DCD is to use a small log disk, referred to as cache-disk, as a secondary disk cache to optimize write performance. While the cache

small (32 KB) prediction cache we can get an effective main memory access time that is close to the access time of larger secondary caches.

As processor speeds increase and memory latency be-comes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of current set-associative caches is reduced be-cause programs exhibit a non-uniform distribution of mem-ory accesses across

in the virtual-memory domain to cope with disk access latencies. Future systems will need to employ similar techniques to deal with DRAM latencies. This paper presents a practical, fully associative, software-managed secondary cache system that provides performance competitive with or superior to traditional

This paper presents an instruction cache prefetching mechanism capable of prefetching past branches in multiple-issue processors. Such processors at high clock rates often use small instruction caches which have significant miss rates. Prefetching from secondary cache can hide the instruction cache

-items are consumed from the heads of the queues. Since the number of unconsumed items may exceed memory buffer size, some items in the queues need to be spilled to secondary storage and later moved back into memory for consumption. We provide online queue-caching algorithms under a number of interesting cost models.

We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a relatively small DRAM, which includes a primary file buffer cache, and a flash memory secondary file buffer cache. Compared

We propose a secondary cache architecture that combines a predictive fetch strategy with a distributed cache to build a high performance memory system. The cache is partitioned into smaller units and distributed evenly in the main memory space. The architecture o#ers high bandwidth between

via tag bits, object- and page-based locking, range checking, object to virtual mapping function, and use of a secondary descriptor cache. The cache design results in a processor which is no slower than conventional processors based on virtual memory. The design is then extensively analysed

Figure 1: Three example scenes rendered using sample caching. Using caching during walkthrough animations allows for reusing shading results in subsequent frames, and to reduce the number of secondary rays to be cast by more than an order of magnitude. Despite tremendous progress in the last few