This paper presents an integrated, fully associative, wide Cached-DRAM (WCDRAM). We propose a fully associative cache with very large blocks (1KB-8KB) but few entries (32-128), integrated with the DRAM array. By doing this, we exploit the internal bandwidth inherent in DRAM access. A single row

Radio Frequency Identification (RFID) based item-level tracking holds the promise of revolutionizing supply-chain, retail store, and asset management applications. However, the high volume of data generated by item-level tracking poses challenges to the applications as well as to backend databases

Traditional client-server applications relegate query and persistence operations on their data to database systems. The database system operates on data in the form of rows and tables, while the application operates on data in terms of higher-level programming language constructs (classes

demand. As we show in this work, memory requests go through several phases. In each phase, programs tend to access a single bank most of the time. We exploit this repetitive behavior and improve the concurrency level for memory read and write operations. We do so by assigning idle row buffers to more

Abstract—DRAM-based main memories have read operations that destroy the read data, and as a result, must buffer large amounts of data on each array access to keep chip costs low. Unfortunately, system-level trends such as increased memory contention in multi-core architectures and data mapping

Abstract: This paper proposes a universal architecture of Security Management Model (SMM) for integrating security features namely low-level access control at row and column level of relational legacy databases using XML as an integration medium. The proposed model integrates and then rearranges

Existing techniques for traversing a polygon generate frag-ments one (or more) rows or columns at a time. (A fragment is all the information needed to paint one pixel of the polygon.) This order is non-optimal for many operations. For example, most frame buffers are tiled into rectangular pages

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, an extensible framework that provides system-level content and event information to application developers. Its use is demonstrated in a multi-impairment case study achieving automatic row-column scanning with audio feedback. SWAT presents strengths usable in several other system-wide contexts that empower

DRAM-based main memories have read operations that destroy the read data, and as a result, must buffer large amounts of data on each array access to keep chip costs low. Unfortunately, system-level trends such as increased memory contention in multi-core architectures and data mapping schemes