this paper to understand the extent to which this feeling corresponds to reality . We selected a set of reference RISC based systems to represent RISC technology, and identified a set of basic image processing tasks to represent the image processing domain. We measured the performance and studied

The IBM SP is one of the most powerful commercial MPPs, yet, in spite of its fast processors and high network bandwidth, the SP’s communication latency is inferior to older machines such as the TMC CM-5 or Meiko CS-2. This paper investigates the use of Active Messages (AM) communication primitives as an alternative to the standard message passing in order to reduce communication overheads and to offer a good building block for higher layers of software. The first part of this paper describes an implementation of Active Messages (SP AM) which is layered directly on top of the SP’s network adapter (TB2). With comparable bandwidth, SP AM’s low overhead yields a round-trip latency that is 40 % lower than IBM MPL’s. The second part of the paper demonstrates the power of AM as a communication substrate by layering Split-C as well as MPI over it. Split-C benchmarks areusedtocomparetheSPtootherMPPsandshowthatlow message overhead and high throughput compensate for SP’s high network latency. The MPI implementation is based on the freely available MPICH version and achieves performance equivalent to IBM’s MPI-F on the NAS benchmarks. 1

The IBM SP is one of the most powerful commercial MPPs, yet, in spite of its fast processors and high network bandwidth, the SP's communication latency is inferior to older machines such as the TMC CM-5 or Meiko CS-2. This paper investigates the use of Active Messages (AM) communication primitives as an alternative to the standard message passing in order to reduce communication overheads and to o er a good building block for higher layers of software. The rst part of this paper describes an implementation of Active Messages (SP AM) which islayered directly on top of the SP's network adapter (TB2). With comparable bandwidth, SP AM's low overhead yields a round-trip latency that is 40% lower than IBM MPL's. The second part of the paper demonstrates the power of AM as a communication substrate by layering Split-C as well as MPI over it. Split-C benchmarks are used to compare the SP to other MPPs and show that low message overhead and high throughput compensate for SP's high network latency. The MPI implementation is based on the freely available MPICH version and achieves performance equivalent to IBM's MPI-F on the NAS benchmarks. 1

Using the PVM programming environment for parallel applications, we have parallelized a simulation of the two--dimensional Ising Model on a cluster of IBM RISC System/6000 1 workstations connected by a Token Ring (16Mb/sec) and by Serial Optical Channels (220 Mb/sec) via a NSC 2 DX Router

system, or applications programs. A prototype system was constructed for HP’s PA-RISC instruction-set architecture. Using this prototype, engineering issues and performance implications of the approach were explored.

language SPARQL entail efficiency and scalability challenges for complex queries including long join paths. This paper presents the RDF-3X engine, an implementation of SPARQL that achieves excellent performance by pursuing a RISC-style architecture with a streamlined architecture and carefully designed

An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits

-thread performance and supports virtual dynamic threads. A commercial RISC-based implementation of APRIL and a run-time software system that can switch contexts in about 10 cycles is described. Measurements taken for several parallel applications on an APRIL simulator show that the overhead for supporting parallel

This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both ram and rom are strong, the size of compiled code is increasingly important. Similarly, in mobile and network computing, the need

and sensing algorithms. RISC systems should be cost-effective and reliable, and easy to setup and reconfigure. They should also be flexible enough to support small batch sizes and rapid changes in part design needed in forthcoming flexible-agile manufacturing systems. The RISC acronym, borrowed from computer