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Caisson: A Hardware Description Language for Secure Information Flow

by Xun Li, Mohit Tiwari, Jason K. Oberg, Vineeth Kashyap, Frederic T. Chong, Timothy Sherwood, Ben Hardekopf - IN PROCEEDINGS OF PROGRAMMING LANGUAGE DESIGN AND IMPLEMENTATION (PLDI 2011 , 2011
"... Information flow is an important security property that must be incorporated from the ground up, including at hardware design time, to provide a formal basis for a system’s root of trust. We incorporate insights and techniques from designing information-flow secure programming languages to provide a ..."
Abstract - Cited by 16 (6 self) - Add to MetaCart
allows for an expressive, provably-secure HDL that operates at a familiar level of abstraction to the target audience of the language, hardware architects. We have implemented a compiler for Caisson that translates designs into Verilog and then synthesizes the designs using existing tools. As an example

Enhancing security via provably trustworthy hardware intellectual property

by Eric Love, Yier Jin, Yiorgos Makris - in IEEE International Symposium on Hardware-Oriented Security and Trust , 2011
"... Abstract—We introduce a novel hardware intellectual property acquisition protocol, show how it can support the transfer of provably trustworthy modules between hardware IP producers and consumers, and discuss what it might mean for a device to be considered “secure. ” Specifically, we demonstrate th ..."
Abstract - Cited by 2 (0 self) - Add to MetaCart
Abstract—We introduce a novel hardware intellectual property acquisition protocol, show how it can support the transfer of provably trustworthy modules between hardware IP producers and consumers, and discuss what it might mean for a device to be considered “secure. ” Specifically, we demonstrate

A Practical Testing Framework for Isolating Hardware Timing Channels

by Jason Oberg, Sarah Meiklejohn, Timothy Sherwood, Ryan Kastner
"... Abstract—This work identifies a new formal basis for hardware information flow security by providing a method to separate timing flows from other flows of information. By developing a framework for identifying these different classes of information flow at the gate-level, one can either confirm or r ..."
Abstract - Cited by 2 (2 self) - Add to MetaCart
or rule out the existence of such flows in a provable manner. To demonstrate the effectiveness of our presented model, we discuss its usage on a practical example: a CPU cache in a MIPS processor written in Verilog HDL and simulated in a scenario which accurately models previous cache-timing attacks. We
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