Results 1 - 10 of 609

Detailed routing architectures for embedded programmable logic IP cores

by Peter Hallschmid, Steven J. E. Wilton - In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays , 2001
"... As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be realized using programmable logic cores. These cores are blocks of programmable logic that can be embedded into a fixed-funct ..."
Abstract - Cited by 10 (0 self) - Add to MetaCart
As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be realized using programmable logic cores. These cores are blocks of programmable logic that can be embedded into a fixed

Programmable Logic IP Cores in SoC Design: Opportunities and Challenges

by Steven J.E. Wilton, Resve Saleh , 2001
"... As SoC design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other IP in the SoC design methodology, except that their function can be changed after ..."
Abstract - Cited by 6 (1 self) - Add to MetaCart
As SoC design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other IP in the SoC design methodology, except that their function can be changed

Larrabee: a many-core x86 architecture for visual computing

by Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Toni Juan, Pat Hanrahan - In SIGGRAPH ’08: ACM SIGGRAPH 2008 papers , 2008
"... Abstract 123 This paper presents a many-core visual computing architecture code named Larrabee, a new software rendering pipeline, a manycore programming model, and performance analysis for several applications. Larrabee uses multiple in-order x86 CPU cores that are augmented by a wide vector proces ..."
Abstract - Cited by 279 (12 self) - Add to MetaCart
processor unit, as well as some fixed function logic blocks. This provides dramatically higher performance per watt and per unit of area than out-of-order CPUs on highly parallel workloads. It also greatly increases the flexibility and programmability of the architecture as compared to standard GPUs. A

Logic Programming in the LF Logical Framework

by Frank Pfenning , 1991
"... this paper we describe Elf, a meta-language intended for environments dealing with deductive systems represented in LF. While this paper is intended to include a full description of the Elf core language, we only state, but do not prove here the most important theorems regarding the basic building b ..."
Abstract - Cited by 188 (53 self) - Add to MetaCart
and it is solely the programmer's responsibility to construct object-logic proofs where they are needed. Secondly, the partial correctness of many meta-programs with respect to a given logic can be expressed and proved by Elf itself (see the example in Section 5). This creates the possibilit...

Non-Rectangular Embedded Programmable Logic Cores

by Tony Yau-wai Wong , 2002
"... As System-on-a-Chip (SoC) design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other intellectual property (IP) in the SoC design methodology, exce ..."
Abstract - Cited by 3 (0 self) - Add to MetaCart
As System-on-a-Chip (SoC) design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other intellectual property (IP) in the SoC design methodology

EMBEDDED PROGRAMMABLE LOGIC CORES

by James Cheng-huan Wu , 2004
"... As integrated circuits become increasingly more complex and expensive, the ability to make post-fabrication changes will become much more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of “hard ” macro layouts. An ..."
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As integrated circuits become increasingly more complex and expensive, the ability to make post-fabrication changes will become much more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of “hard ” macro layouts

Soft Programmable Logic Cores

by Andy Yan, Dr. Steven Wilton
"... • Propose new architectural family for synthesizable programmable logic cores – Basic logic element: Product-term array block – 35 % density, 72 % speed improvement compared to LUT-based architecture • Provide Sequential Circuit support • Describe proof-of-concept chip employing novel architecture ..."
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• Propose new architectural family for synthesizable programmable logic cores – Basic logic element: Product-term array block – 35 % density, 72 % speed improvement compared to LUT-based architecture • Provide Sequential Circuit support • Describe proof-of-concept chip employing novel architecture

Architectures and Algorithms for Synthesizable Embedded Programmable Logic Cores

by Noha Kafafi , Kimberly Bozman , Steven J. E. Wilton , 2003
"... As integrated circuits become more and more complex, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of a "hard" layout. In this pape ..."
Abstract - Cited by 21 (4 self) - Add to MetaCart
As integrated circuits become more and more complex, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of a "hard" layout

Design considerations for soft embedded programmable logic cores

by Steven J. E. Wilton, Senior Member, Noha Kafafi, James C. H. Wu, Kimberly A. Bozman, Victor O. Aken’ova, Resve Saleh, Senior Member - IEEE J. Solid-State Circuits , 2005
"... Abstract—As integrated circuits become increasingly more complex and expensive, the ability to make post-fabrication changes will become much more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of “hard ” rectangu ..."
Abstract - Cited by 14 (3 self) - Add to MetaCart
Abstract—As integrated circuits become increasingly more complex and expensive, the ability to make post-fabrication changes will become much more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of “hard

Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs

by unknown authors
"... We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition probabilities (profiles) at the inputs of circuits with full-scan using testability metrics based on the targeted fault mod ..."
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We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition probabilities (profiles) at the inputs of circuits with full-scan using testability metrics based on the targeted fault
Results 1 - 10 of 609