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19
Dynamo: A Transparent Dynamic Optimization System
- ACM SIGPLAN NOTICES
, 2000
"... We describe the design and implementation of Dynamo, a software dynamic optimization system that is capable of transparently improving the performance of a native instruction stream as it executes on the processor. The input native instruction stream to Dynamo can be dynamically generated (by a JIT ..."
Abstract
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Cited by 479 (2 self)
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not require multiple runs, or any special compiler, operating system or hardware support. The Dynamo prototype presented here is a realistic implementation running on an HP PA-8000 workstation under the HPUX 10.20 operating system.
Functional Verification of the HP PA 8000 Processor
"... This paper describes the enhanced functional verification tools and processes that were required to address the daunting microarchitectural complexity of the PA 8000 ..."
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This paper describes the enhanced functional verification tools and processes that were required to address the daunting microarchitectural complexity of the PA 8000
Four-Way Superscalar PA-RISC Processors: The HP PA 8000 and PA 8200 PA-RISC CPUs feature an aggressive four-way superscalar implementation, speculative execution, and on-the-fly instruction reordering
, 1997
"... This paper discusses the objectives for the design of these processors, some of the key architectural features, implementation details, and system performance. The operation of the instruction reorder buffer (IRB), 5 which provides out-of-order execution capability, will also be described ..."
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This paper discusses the objectives for the design of these processors, some of the key architectural features, implementation details, and system performance. The operation of the instruction reorder buffer (IRB), 5 which provides out-of-order execution capability, will also be described
Timing Attack: What Can Be Achieved By A Powerful Adversary?
- The 20th symposium on Information Theory in the Benelux
, 1999
"... INTRODUCTION Implementations of cryptographic algorithms tend to perform computations in non-constanttime, due to performance optimizations. If such operations involve secret parameters, these timing variations can leak some information and, provided enough knowledge of the implementation is at hand ..."
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Cited by 8 (1 self)
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them on a parallel architecture on 4 processors PA8000 @ 180Mhz
Instructions Scheduling for Highly Super-scalar Processors
, 1997
"... Super-scalar processors can execute multiple instructions out-of-order per cycle and speculatively execute instructions through branches. Such processors invalidate many of the assumptions of traditional instruction scheduling. This article analyzes the impact of super-scalar processor architectu ..."
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Cited by 1 (0 self)
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to benchmarks, and it is shown that traditional depthfirst instruction scheduling performs badly compared to a variety of breadth-first instruction scheduling heuristics. Modern high-performance microprocessors, such as the HP PA-8000[12] or the PowerPC 620[4], are all super-scalar, meaning that they can
unknown title
"... The PA-8500 is the newest member of the PA-RISC family of processors. The design is based on the PA-8000 and PA-8200 processors, but is implemented in a.25 micron process. The new process allows the large first level caches to be moved on-chip so that the frequency can be boosted without the need to ..."
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The PA-8500 is the newest member of the PA-RISC family of processors. The design is based on the PA-8000 and PA-8200 processors, but is implemented in a.25 micron process. The new process allows the large first level caches to be moved on-chip so that the frequency can be boosted without the need
Evaluating A Multithreaded Superscalar Microprocessor Versus A Multiprocessor Chip
- 4th PASA Workshop, Juelich, World Sc. Publ
, 1996
"... This paper examines implementation techniques for future generations of microprocessors. While the wide superscalar approach, which issues 8 and more instructions per cycle from a single thread, fails to yield a satisfying performance, its combination with techniques that utilize more coarse-grained ..."
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Cited by 5 (4 self)
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instruction issue technique. DEC Alpha 21164, PowerPC 604 and 620, MIPS R10000, Sun UltraSparc and HP PA-8000 issue up to four instructions per cycle from a single thread. VLSI-technology will allow future generations of microprocessors to exploit instruction-level parallelism up to 8 instructions per cycle
Implementation of Multiple Pagesize Support in HP-UX
, 1998
"... To reduce performance degradation from Translation Lookaside Buffer (TLB) misses without significant increase in TLB size, most modern processors implement TLBs that support multiple pagesizes. For example, Hewlett-Packard's PA-8000 processor allows 8 hardware pagesizes, in multiples of four, r ..."
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Cited by 11 (0 self)
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To reduce performance degradation from Translation Lookaside Buffer (TLB) misses without significant increase in TLB size, most modern processors implement TLBs that support multiple pagesizes. For example, Hewlett-Packard's PA-8000 processor allows 8 hardware pagesizes, in multiples of four
Comparison of Finite-Difference and SPICE Tools for Thermal Modeling of the Effects of Nonuniform Power Generation in High-Power
, 1998
"... This paper describes a thermal study of junction temperature variation across the surface of a large CPU resulting from nonuniform power generation. Results from Flotherm finite-difference thermal analysis software were compared to results from a SPICE simulation. Both simulations provided results c ..."
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to significant variations in junction temperature across the die surface. If these temperature gradients are not fully understood or anticipated, product reliability may be degraded. The HP PA 8000 microprocessor is a high-performance implementation of HP’s PA-RISC computer architecture. 1 It is the central
fcc Fork95 Compiler Reference Manual
"... others have been completely rewritten from scratch. I have also completely rewritten the compiler driver. Finally,version 1.9 features a graphical trace file visualization tool, trv. This report describes installation, use, and implementation principles of fcc. 1 Installing fcc 1.1 Hardware platform ..."
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is currently in a testing stage by the SB-PRAM group at Saarbr"ucken. Prof. E. Mayordomo from the University of Zaragoza, Spain, reports on a successful installation of both compilerand system tools on an HP K250/3 with 3 PA8000 processors (512 MB memory and 20 Gb disk) under HPUX 10.20. Please notify
Results 1 - 10
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