LLing the processor inLcrcoIlnccLioll sLrucLun ~ La be programmed. This new kind of programmrning is explained. Algorithms arc presented for several intercollIlecLion patterns including the Lorus and Lhe complcLc binary Lree and general embedding straLegies arc idenlificd. 'The rcsccrch dcse,ibed herein is par

Servers that consist of multiple nodes and sockets are in-terconnected together with a high-bandwidth, low latency processor interconnect network, such as Intel QPI or AMD Hypertransport technologies. The different nodes exchange packets through routers which communicate with other routers. A key

The majority of existing interprocessor connection networks are plagued by poor topological properties that result in large memory latencies for DSM (Distributed Shared-Memory) computers. On the other hand, scalable networks with very good topological properties are often impossible to build because of their prohibitively high VLSI (e.g., wiring) complexity.

Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network

Parallel processor interconnection networks traditionally have been designed from a known set of topologies based on geometric shapes, called conceptual topologies. However, conceptual topologies only explore a very small portion of the solution space, so they may not produce a very desirable

A general framework for architectural design of large hierarchical multiprocessor systems under rapidly changing packaging, processor, and interconnection technologies is presented. In recent years processor boards with larger area (A) and greater pinouts are becoming feasible. Board

In this paper we present a general framework for architectural design of large hierarchical multiprocessor systems under rapidly changing packaging, processor, and interconnection technologies. Processor boards with larger area (A) and greater pinouts are becoming feasible. Board interconnection

This paper studies a flexible hierarchic design approach of large processor networks with distributed media access. The cluster-based interconnection combines passive metal buses and passive optical star couplers at two hierarchic levels, independently employing interleaved TDMA for conflict

Abstract not found

Scalable shared-memory multiprocessors distribute memory among the processors and use scalable interconnection networks to provide high bandwidth and low latency communication. In addition, memory accesses are cached, buffered, and pipelined to bridge the gap between the slow shared memory