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982
Shoestring: Probabilistic Soft Error Reliability on the Cheap
"... Aggressive technology scaling provides designers with an ever increasing budget of cheaper and faster transistors. Unfortunately, this trend is accompanied by a decline in individual device reliability as transistors become increasingly susceptible to soft errors. We are quickly approaching a new er ..."
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Cited by 24 (3 self)
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Aggressive technology scaling provides designers with an ever increasing budget of cheaper and faster transistors. Unfortunately, this trend is accompanied by a decline in individual device reliability as transistors become increasingly susceptible to soft errors. We are quickly approaching a new
Iterative (turbo) soft interference cancellation and decoding for coded CDMA
- IEEE Trans. Commun
, 1999
"... Abstract — The presence of both multiple-access interference (MAI) and intersymbol interference (ISI) constitutes a major impediment to reliable communications in multipath code-division multiple-access (CDMA) channels. In this paper, an iterative receiver structure is proposed for decoding multiuse ..."
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Cited by 456 (18 self)
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computational complexity. A low-complexity SISO multiuser detector is developed based on a novel nonlinear interference suppression technique, which makes use of both soft interference cancellation and instantaneous linear minimum mean-square error filtering. The properties of such a nonlinear interference
Soft Error Resilience of Probabilistic Inference Applications
- IN PROCEEDINGS OF THE WORKSHOP ON SYSTEM EFFECTS OF LOGIC SOFT ERRORS
, 2006
"... With shrinking device size and increasing complexity, soft errors are becoming an issue in the reliability of digital systems. To make efficient robust systems, it is important to understand how soft errors affect the quality of output for the target applications. Probabilistic inference applicatio ..."
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Cited by 16 (0 self)
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With shrinking device size and increasing complexity, soft errors are becoming an issue in the reliability of digital systems. To make efficient robust systems, it is important to understand how soft errors affect the quality of output for the target applications. Probabilistic inference
Probabilistic Soft Error Detection Based on Anomaly Speculation
, 2011
"... Microprocessors are becoming increasingly vulnerable to soft errors due to the current trends of semiconductor technology scaling. Traditional redundant multi-threading architectures provide perfect fault tolerance by re-executing all the computations. However, such a full re-execution technique si ..."
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Microprocessors are becoming increasingly vulnerable to soft errors due to the current trends of semiconductor technology scaling. Traditional redundant multi-threading architectures provide perfect fault tolerance by re-executing all the computations. However, such a full re-execution technique
Accurate reliablity evaluation and enhancement via probabilistic transfer matrices
- In Proc
, 2005
"... Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on probabilistic transfer matrices (PTMs). In particular, we apply them to evaluate circuit reliability in the presence of s ..."
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Cited by 43 (5 self)
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Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on probabilistic transfer matrices (PTMs). In particular, we apply them to evaluate circuit reliability in the presence
Fingerprinting: Bounding Soft-Error Detection Latency and Bandwidth
- In Proc. of the Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS
, 2004
"... Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an e#cient error detection technique, called fingerprinting, that detects di#erences in execution across a dual modular redundant (DMR) processor pair. Finger ..."
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Cited by 80 (8 self)
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Recent studies have suggested that the soft-error rate in microprocessor logic will become a reliability concern by 2010. This paper proposes an e#cient error detection technique, called fingerprinting, that detects di#erences in execution across a dual modular redundant (DMR) processor pair
Error Resilient System Architecture (ERSA) For Probabilistic Applications
"... Abstract—Probabilistic applications such as data mining, image recognition and case synthesis (often referred to as Recognition, Mining and Synthesis or RMS), constitute a class of emerging applications expected to drive future demand for computational capacity. This paper describes the design and p ..."
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Cited by 5 (0 self)
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and prototyping of a low-cost Error-Resilient System Architecture (ERSA), specifically targeted for these applications, featuring a combination of cheap, unreliable compute power together with a small fraction of reliable processor cores for running system software, controlling application flow, and recovering
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
- IEEE Transactions on Dependable and Secure Computing, 1(2):128–143, April-June
"... Abstract—Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in highperformance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rat ..."
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Cited by 88 (1 self)
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rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a
Probabilistic Soft Error Rate Estimation from Statistical
- SEU Parameters,” in Proc. 17th IEEE North Atlantic Test Workshop
, 2008
"... Nanometer CMOS VLSI circuits are highly sensitive to soft errors, also known as single-event upsets (SEU) that induce current pulses at random times and at random locations in a digital circuit. Environmental causes of SEU include cosmic radiation and high-energy particles. Our neutron induced soft ..."
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Cited by 1 (1 self)
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Nanometer CMOS VLSI circuits are highly sensitive to soft errors, also known as single-event upsets (SEU) that induce current pulses at random times and at random locations in a digital circuit. Environmental causes of SEU include cosmic radiation and high-energy particles. Our neutron induced soft
On the Reliable Performance of Sequential Adders for Soft Computing
"... Abstract — Addition is a significant operation in soft computing; several sequential adder designs have been proposed in the technical literature. These adders show different operational profiles; some of them are inspired by biological networks or the probabilistic nature of nanometric devices (suc ..."
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Cited by 1 (1 self)
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(such as the Lower-part OR Adder (LOA) and the Probabilistic Full Adder (PFA)). This paper deals with the reliability assessment and comparison of these sequential adder implementations. A new metric referred to as the mean error distance (MED) is proposed as a unified figure for evaluating
Results 1 - 10
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982