"... In PAGE 3: ... In summary, there are strong reasons to suspect that these estimates are not correct. In this case, what would explain the high estimates for the output-average hours elasticity found by previous works? Table1 lists these results. With the exception of Leslie and White (1980), they all find that the output-employment elasticity is smaller than the output-average hours elasticity.... ..."

"... In PAGE 14: ...4 Table 1 summarizes the key characteristics of the datasets used in this study. Table2 summarizes the original results reported (Quinlan, 1993). These include model- trees (MT), which are regression trees with linear ts at the terminal nodes; neural nets (NNET); 3-nearest neighbors (3-nn); and the combined results of model-trees and 3-nearest neighbors (MT/3-nn).... ..."

"... In PAGE 14: ... 4 Table 1 summarizes the key characteristics of the datasets used in this study. Table2 summarizes the original results reported #28Quinlan, 1993#29. These include model- trees #28MT#29, which are regression trees with linear #0Cts at the terminal nodes; neural nets #28NNET#29; 3-nearest neighbors #283-nn#29; and the combined results of model-trees and 3-nearest neighbors #28MT#2F3-nn#29.... ..."

"... In PAGE 5: ... However, in [15] this transformation was used to increase task-level parallelism inside application networks. The sim- ulation results in cycles and approximative simulation times are given in Table1 . The FPGA case is a reference to both mapping and very detailed VHDL cycle accurate simula- tion [15] [6].... In PAGE 6: ... The clarification of the later observation requires a bit more explanation. In [3] we conducted an exploration on a conceptual level about the possible causes for the in- accurate results shown in Table1 . The preliminary results showed that inaccuracies are mainly due to the lack of the modelling capabilities in [4].... ..."

"... In PAGE 5: ... However, in [15] this transformation was used to increase task-level parallelism inside application networks. The simulation re- sults in cycles and approximative simulation times are given in Table1 . As one can see, although in the SPADE case sim- ulations took signi cantly less time than in the FPGA case, the accuracy of the SPADE simulations was very low.... In PAGE 6: ... Our results a0a2a1a4a3a6a5a8a7a10a9 a11 a13 a15 a16 a18 a1a4a19 unfold1 unfold3 unfold5 t case 1 107951 36111 22590 a1 10s case 2 41073 13787 8653 a1 10s case 3 29458 9884 6202 a1 10s The results shown in Table 2 lead to the following ob- servations: (1) the SPU models very accurately model the reality, and (2) the SPU models are capable to better rep- resent both application and architecture properties than the TD models used in [4]. We assume that the reality is repre- sented by the FPGA numbers given in Table1 . By compari- son of the FPGA numbers with the numbers for case 3 given in Table 2, we support the former observation.... In PAGE 6: ... The clari ca- tion of the later observation requires a bit more explanation. In [3] we conducted an exploration on a conceptual level about the possible causes for the inaccurate results shown in Table1 . The preliminary results showed that inaccura- cies are mainly due to the lack of the modelling capabilities in [4].... ..."

"... In PAGE 5: ... However, in [15] this transformation was used to increase task-level parallelism inside application networks. The simulation re- sults in cycles and approximative simulation times are given in Table1 . As one can see, although in the SPADE case sim- ulations took significantly less time than in the FPGA case, the accuracy of the SPADE simulations was very low.... In PAGE 6: ... Our results C6CTD8DBD3D6CZAX BVCPD7CTAZ unfold1 unfold3 unfold5 t case 1 107951 36111 22590 AK10s case 2 41073 13787 8653 AK10s case 3 29458 9884 6202 AK10s The results shown in Table 2 lead to the following ob- servations: (1) the SPU models very accurately model the reality, and (2) the SPU models are capable to better rep- resent both application and architecture properties than the TD models used in [4]. We assume that the reality is repre- sented by the FPGA numbers given in Table1 . By compari- son of the FPGA numbers with the numbers for case 3 given in Table 2, we support the former observation.... In PAGE 6: ... The clarifica- tion of the later observation requires a bit more explanation. In [3] we conducted an exploration on a conceptual level about the possible causes for the inaccurate results shown in Table1 . The preliminary results showed that inaccura- cies are mainly due to the lack of the modelling capabilities in [4].... ..."

"... In PAGE 6: ... We used a 10-fold cross validation for our experiment. Table4 shows our results are much more accurate than the previous results. 5.... ..."

"... In PAGE 14: ...Table2 shows comparative results for the ve easiest problems solved in [9], which we also solved using the same heuristic as in [9], but without duplicate pruning. The rst column gives the corresponding problem number from Table 3, the second the length of the optimal solution, the third the number of node generations from [9] with FSM pruning, the fourth column the number of nodes generated using the same heuristic but without FSM pruning, and the fth column gives the number of nodes generated with our disjoint pattern database heuristic without FSM pruning.... ..."