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2,316
Precise Exceptions in Asynchronous Processors
- In Proceedings of the 2001 Conference on Advanced Research in VLSI
, 2001
"... The presence of precise exceptions in a processor leads to complications in its design. Some recent processor architectures have sacrificed this requirement for performance reasons at the cost of software complexity. We present an implementation strategy for precise exceptions in asynchronous proces ..."
Abstract
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Cited by 5 (1 self)
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The presence of precise exceptions in a processor leads to complications in its design. Some recent processor architectures have sacrificed this requirement for performance reasons at the cost of software complexity. We present an implementation strategy for precise exceptions in asynchronous
Precise Exception Semantics in Dynamic Compilation
- In Symposium on Compiler Construction
, 2002
"... Maintaining precise exceptions is an important aspect of maintaining compatibility with a legacy architecture. While asynchronous exceptions can be deferred to an appropriate boundary in the code, synchronous exceptions must be taken when they occur. This introduces uncertainty into liveness analysi ..."
Abstract
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Cited by 8 (0 self)
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Maintaining precise exceptions is an important aspect of maintaining compatibility with a legacy architecture. While asynchronous exceptions can be deferred to an appropriate boundary in the code, synchronous exceptions must be taken when they occur. This introduces uncertainty into liveness
Processor Verification with Precise Exceptions and Speculative Execution
"... We describe a framework for verifying a pipelined microprocessor whose implementation contains precise exceptions, external interrupts, and speculative execution. We present our correctness criterion which compares the state transitions of pipelined and non-pipelined machines in presence of exte ..."
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Cited by 55 (4 self)
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We describe a framework for verifying a pipelined microprocessor whose implementation contains precise exceptions, external interrupts, and speculative execution. We present our correctness criterion which compares the state transitions of pipelined and non-pipelined machines in presence
Efficient instruction scheduling with precise exceptions
- In preparation
"... LIMITED DISTRIBUTION NOTICE: This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. Ithas been issued as a Research ..."
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Cited by 2 (2 self)
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LIMITED DISTRIBUTION NOTICE: This report has been submitted for publication outside of IBM and will probably be copyrighted if accepted for publication. Ithas been issued as a Research
Precise Exception Handling for a Self-Timed Processor
- in 1995 International Conference on Computer Design: VLSI in Computers & Processors, (Los Alamitos, CA
, 1995
"... Self-timed systems structured as multiple concurrent processes and communicating through self-timed queues are a convenient way to implement decoupled computer architectures. Machines of this type can exploit instruction level parallelism in a natural way, and can be easily modified and extended. Ho ..."
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Cited by 7 (4 self)
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. However, providing a precise exception model for a self-timed micropipelined processor can be difficult, since the processor state does not change at uniformly discrete intervals. We present a precise exception method implemented for Fred, a self-timed, decoupled, pipelined computer architecture with out
Efficient Implementation of Precise Exception for Processor Based on Pre-detection
"... Abstract—Embedded systems have higher requirements on real-time performance of processor. However exception, which can interrupt normal execution of program, will decrease the processor performance. For improving the exception handling efficiency of processor, a precise exception handling method for ..."
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Abstract—Embedded systems have higher requirements on real-time performance of processor. However exception, which can interrupt normal execution of program, will decrease the processor performance. For improving the exception handling efficiency of processor, a precise exception handling method
Precise Exception Handling in Discontinuous Control Flow Scenarios for Area-Constrained Systems
"... Abstract — Exception handling is one of the most complicated issues in pipelined processors. Several incomplete instructions are in process in the pipeline at any instant in time, and an exception may cause a state change of the processor [5] at any such instant. Prior research efforts have proposed ..."
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proposed mechanisms for precise exception handling, but it is difficult to achieve precise exception handling in minimal area as required by embedded and processing-in-memory systems. This paper presents a correct and efficient exception handling scheme with a modest hardware resource. The presented idea
OUT-OF-ORDER COMMIT LOGIC WITH PRECISE EXCEPTION HANDLING FOR PIPELINED PROCESSORS
"... The major bottleneck in today’s pipelined microprocessors has been data dependencies and branch prediction. Existing approaches have focused on issuing instructions out-of-order but have limited themselves to committing in-order considering the amount of overhead involved. This paper proposes an arc ..."
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an architecture in which instructions are allowed to commit out-of-order thereby increasing the throughput. The problem of precise exception handling in out-of-order commit has also been handled without involving significant hardware overhead. The design proposed in this paper can also be extended in future
Load elimination in the presence of side effects concurrency and precise exceptions
- In Proceedings of the International Workshop on Compilers for Parallel Computing (LCPC’03
, 2003
"... Abstract. Partial redundancy elimination can reduce the number of loads corresponding to field and array accesses in Java programs. The reuse of values loaded from memory at subsequent occurrences of load expressions must be done with care: Precise exceptions and the potential of side effects throug ..."
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Cited by 5 (1 self)
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Abstract. Partial redundancy elimination can reduce the number of loads corresponding to field and array accesses in Java programs. The reuse of values loaded from memory at subsequent occurrences of load expressions must be done with care: Precise exceptions and the potential of side effects
Results 1 - 10
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2,316
