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241
Matlab user’s guide
, 2005
"... This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution, and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portio ..."
Abstract
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Cited by 535 (0 self)
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of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. Intel is a registered trademark of Intel Corporation. PowerPC is a trademark of International Business Machines Corporation. The OPEN
Performance evaluation of the powerpc 620 microarchitecture
- In Proceedings of the 22nd International Symposium on Computer Architecture
, 1995
"... The PowerPC 620 superscalar microprocessor is the most recent and performance leading member of the PowerPC family, which is being jointly developed by IBM and Motorola. The 64-bit 620 represents the most aggressive microarchitecture for superscalar processors to date. It employs a two-level branch ..."
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Cited by 25 (5 self)
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The PowerPC 620 superscalar microprocessor is the most recent and performance leading member of the PowerPC family, which is being jointly developed by IBM and Motorola. The 64-bit 620 represents the most aggressive microarchitecture for superscalar processors to date. It employs a two-level branch
Functional verification methodology for the PowerPC
- 604 microprocessor,” Proc. Design Automation Conf
, 1996
"... Functional (i.e., logic) verification of the current generation of complex, super-scalar microprocessors such as the PowerPC 604 microprocessor presents significant challenges to a project’s verification participants. Simple architectural level tests are insufficient to gain confidence in the quali ..."
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Cited by 18 (0 self)
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Functional (i.e., logic) verification of the current generation of complex, super-scalar microprocessors such as the PowerPC 604 microprocessor presents significant challenges to a project’s verification participants. Simple architectural level tests are insufficient to gain confidence
DAISY: Dynamic Compilation for 100% Architectural Compatibility
, 1997
"... Although VLIW architectures offer the advantages of simplicity of design and high issue rates, a major impediment to their use is that they are not compatible with the existing software base. We describe new simple hardware features for a VLIW machine we call DAISY (Dynamically Architected Instructi ..."
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Cited by 206 (13 self)
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requirements for such a VLIW, to deal with issues including self-modifying code, precise exceptions, and aggressive reordedng of memory references in the presence of strong MP consistency and memory mapped I/O. We have implemented the dynamic parallelization algorithms for the PowerPC architecture. The initial
Mambo a full system simulator for the PowerPC architecture
- ACM SIGMETRICS Performance Evaluation Review
, 2004
"... Mambo is a full-system simulator for modeling PowerPCbased systems. It provides building blocks for creating simulators that range from purely functional to timing-accurate. Functional versions support fast emulation of individual PowerPC instructions and the devices necessary for executing operatin ..."
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Cited by 37 (4 self)
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Mambo is a full-system simulator for modeling PowerPCbased systems. It provides building blocks for creating simulators that range from purely functional to timing-accurate. Functional versions support fast emulation of individual PowerPC instructions and the devices necessary for executing
CGaAs PowerPC FXU
"... The development of a PowerPC TM fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described. Detailed architectural studies led to a design which maximizes performance in a small transistor count implementation. Manufactured in Motorola’s 0.5−µm Complementary Galli ..."
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The development of a PowerPC TM fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described. Detailed architectural studies led to a design which maximizes performance in a small transistor count implementation. Manufactured in Motorola’s 0.5−µm Complementary
CGaAs PowerPC FXU
, 2000
"... The development of a PowerPC fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described. Detailed architectural studies led to a design which maximizes performance in a small transistor count implementa- tion. Manufactured in Motorola's 0.5-m Complementary ..."
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The development of a PowerPC fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described. Detailed architectural studies led to a design which maximizes performance in a small transistor count implementa- tion. Manufactured in Motorola's 0.5-m
Developing an Architecture Validation Suite Application to the PowerPC Architecture
- Architecture,” Proc. 36th Design Automation Conf., ACM
, 1999
"... This paper describes the efforts made and the results of creating an Architecture Validation Suite for the PowerPC architecture. Although many functional test suites are available for multiple architectures, little has been published on how these suites are developed and how their quality should be ..."
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Cited by 3 (1 self)
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This paper describes the efforts made and the results of creating an Architecture Validation Suite for the PowerPC architecture. Although many functional test suites are available for multiple architectures, little has been published on how these suites are developed and how their quality should
SimpleScalar Simulation of the PowerPC Instruction Set Architecture
, 2000
"... In this report, we describe a modification to the SimpleScalar tool set to support the PowerPC ISA. Our work is based on Version 3.0 of the publicly available SimpleScalar tool set. We briefly describe features of the PowerPC ISA relevant to the simulator and provide operating system specific implem ..."
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Cited by 4 (2 self)
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implementation details. We made modifications to the suite of five simulators that model the micro-architecture at different levels of detail. The timing simulator sim-outorder simulates PowerPC binaries on the Register Update Unit (RUU) micro-architecture. The ve simulators were tested by simulating the SPEC
PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620
- IEEE-CS Press, Proceedings of the Sixth International Symposium on High-Performance Computer Architecture
, 2000
"... The paper presents PowerMANNA- a distributed-memory parallel computer system based on the 64-Bit PowerPC processor MPC620. The PowerMANNA node architecture supports all the sophisticated features of the MPC620 and incorporates important architectural concepts that allow us to exploit the performance ..."
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Cited by 1 (0 self)
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The paper presents PowerMANNA- a distributed-memory parallel computer system based on the 64-Bit PowerPC processor MPC620. The PowerMANNA node architecture supports all the sophisticated features of the MPC620 and incorporates important architectural concepts that allow us to exploit
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241
