Results 1 - 10 of 13,839

Table 6. Comparison of power ( W) consump- tion of binary adders implemented using dif- ferent implementation styles

in Fast Low-Energy VLSI Binary Addition
by Keshab K. Parhi 1997
"... In PAGE 7: ...90 CSEL(5, 2, 2, 2, 5) 727.75 dundant binary adder, the tree based redundant bi- nary adder, and a combination of tree and carry select adders have also been investigated for power consump- tion and the results are summarized in Table6 . The results show that the RB adder in Fig.... ..."
Cited by 12

Table 3: Performance comparison between C_style and OOP_style for all kernels

in Evaluating Performance and Power of Object-Oriented vs. Procedural Programming in Embedded Processors
by Alexander Chatzigeorgiou, George Stephanides
"... In PAGE 7: ...50 ARM Debugger Trace file Profiler #instructions/type Base Energy Cost Overhead Energy Cost TOTAL Processor Cost Code size RAM requirements #instructions #cycles #memory accesses compile execute Data Memory Energy Instruction Memory Energy Memory Power Model Fig. 1: Experiment set up for evaluating performance and power Experimental results concerning the code size of each kernel, the number of executed instructions and cycles are given in Table3 for all OOPACK kernels. As it can be observed, the OOP programming style has a larger impact on the resulting code size than on the number of executed instructions.... ..."

Table2: Power consumption comparisons.

in High-Speed Cordic Implementations Using Advanced Circuit Techniques
by Gunok Jung, Seonki Kim, Gerald E. Sobelman
"... In PAGE 4: ...9 % 45.3 % The average power dissipation during the propagation delay time for each of the circuit design styles is given in Table2 . In order to provide a fair comparison, the circuits required to generate the local clock phases in each case are included in the power results.... ..."

Table 1. Comparison of the Leakage Power Models with SPICE

in Leakage Power Estimation in SRAMs
by Mahesh Mamidipaka, Kamal Khouri, Nikil Dutt, Magdy Abadir
"... In PAGE 13: ...Table 1. Comparison of the Leakage Power Models with SPICE Table1 shows the comparison across different SRAMs used in an industrial e500 processor core design. The actual leakage power numbers and the names of the array are not shown because they are Motorola proprietary data and cannot be published.... In PAGE 14: ... SRAMs 3-7 mostly correspond to the typical im- plementation styles illustrated in the Section 4. From Table1 the error margin varies from -23.... ..."

Table 1: Power consumption and reduction vs. area and slack for design1.

in Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths
by M. Münch, B. Wurth, R. Mehra, J. Sproch, N. Wehn 2000
"... In PAGE 7: ... Power estimates were ob- tained using DesignPower [8]. Table1 summarizes the results for design1 for the non-isolated design, the isolated design using different iso- lation styles (i.e.... ..."
Cited by 14

Table 1: Power consumption and reduction vs. area and slack for design1.

in Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths
by M. Münch, B. Wurth, R. Mehra, J. Sproch, N. Wehn 2000
"... In PAGE 7: ... Power estimates were ob- tained using DesignPower [8]. Table1 summarizes the results for design1 for the non-isolated design, the isolated design using different iso- lation styles (i.e.... ..."
Cited by 14

Table 2 Logic family Average output

in A VLSI Array Architecture for Hough Transform
by K. Maharatna, Swapna Banerjee 2001
"... In PAGE 5: ... A performance comparison of the TGL design style with the conventional CMOS, NMOS pass transistor and Domino CMOS logic style is carried out using an XOR structure. The simulated results are shown in Table2 , which reveals that the TGL style exhibits somewhat better power and delay performance than the CMOS style. The NMOS pass transistor style shows less power consumption than the TGL but they are not suitable for sea of gates design style as they leads to an wastage of prefabricated PMOS transistors.... In PAGE 25: ... The CORDIC arithmetic function. Table2 . Comparison of different logic families using the XOR structure.... ..."
Cited by 2

Table 1: An example of CSQ table style.

in Guidelines for Authors of CSQ
by Gerhard Strube
"... In PAGE 4: ... Please use horizontal lines in tables, but not vertical ones. Table1 gives an example: Table 1: An example of CSQ table style.... ..."

Table 1: An example of CSQ table style.

in unknown title
by unknown authors
"... In PAGE 4: ... Please use horizontal lines in tables, but not vertical ones. Table1 gives an example: Table 1: An example of CSQ table style.... ..."

Table 1. Power Conditioning (Specification)

in CHRISTIAN-ALBRECHTS-UNIVERSITÄT
by Michael Hanus, Bernd Braßel (hrsg, Bericht Nr, Programmiersprachen Und Rechenkonzepte, Michael Hanus, Bernd Braßel (hrsg, Spezifikation Entwurf, Validierung Verifikation 707
"... In PAGE 25: ...Curry JS JSO lines bytes lines bytes lines bytes posSum 1 21 19 278 3 63 isEmail 27 654 183 3050 77 1598 person 71 1624 404 6546 126 2777 exam 102 2333 629 10072 211 4613 Table1 . Code size of some programs button.... In PAGE 25: ... This is implemented by the use of different styles for the error elements that is changed by the JavaScript code (see Section 2). In order to provide an impression of the size of the generated JavaScript code, Table1 contains the results of compiling some example programs from Curry into JavaScript. The columns contain the sizes of the source Curry pro- gram (including all dependent functions but without comments), the generated JavaScript code without optimization (JS), and the generated JavaScript code including optimizations to reduce the code size (JSO).... ..."
Results 1 - 10 of 13,839