that enhances power-awareness and finally to illustrate the impact of such re-engineering. By applying power-awareness formalisms to systems ranging from multipliers to variable voltage processors, we demonstrate increases in energy efficiency of 60%-200%. 1. Introduction A system paradigm that has been

Abstract. The paper describes a formal approach for designing and rea-soning about power-constrained, timed systems. The framework is based on process algebra, a formalism that has been developed to describe and analyze communicating concurrent systems. The proposed extension al-lows the modeling

This paper describes low-voltage RAM designs for stand-alone and embedded memories in terms of signal-to-noise-ratio designs of RAM cells and subthreshold-current reduction. First, structures and areas of current DRAM and SRAM cells are discussed. Next, low-voltage peripheral circuits that have been proposed so far are reviewed with focus on subthreshold-current reduction, speed variation, on-chip voltage conversion, and testing. Finally, based on the above discussion, a perspective is given with emphasis on needs for high-speed simple non-volatile RAMs, new devices/circuits for reducing active-mode leakage currents, and memory-rich SOC architectures. Keywords subthreshold current, DRAM and SRAM cells, gain cells, peripheral circuits, gate-source/substrate-source back-biasing, multi-VT, on-chip voltage converters, testing, non-volatile RAMs, memory-rich architectures.

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to consume minimal energy during power-up, sleep, idle and underloaded conditions, many Dynamic Voltage Scaling (DVS) techniques have been proposed. In this paper, we propose a technique based on the resource reservation paradigm. The paradigm is extended to cope with shared resources and critical sections

For new embeddedsystems to operate under an increasingly diverse range of power and performance constraints, they must be poweraware, not just low-power. That is, they must track their power sources and the changing constraints imposed by the environment.

on the fusion center, the computation load at the sensor nodes is limited, which is desirable for power-aware systems. Last, the performance of the new tracking algorithm in various tracking scenarios is thoroughly studied and compared with standard tracking methods. As shown in the theory and demonstrated

Abstract. More than ever, design methodologies for embedded systems need to support design space exploration in order to experiment with various po-tential HW/SW solutions. Our exploration tool, "Design Trotter", has been designed to evaluate area (A) and time (T) parameters of generic

, voltage and the FIFO sizes to minimize the power consumption. For small problem size, we show that our approach finds solutions which are close to optimal. The power aware interconnect channel synthesis is affected by the system parameters like the data production rate and data consumption rate

Abstract — The goal of the PAWiS project is to develop both, efficient system architectures and the related design methodology for power aware Wireless Sensor and Actor Network nodes that allow for capturing inefficiencies in every aspect of the system. These aspects include all layers