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Performance Tradeoffs In Multithreaded Processors
- IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
, 1991
"... ... utilization. By maintaining multiple process contexts in hardware and switching among them in a few cycles, multithreaded processors can overlap computation with memory accesses and reduce processor idle time. This paper presents an analytical performance model for multithreaded processors th ..."
Abstract
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Cited by 129 (5 self)
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... utilization. By maintaining multiple process contexts in hardware and switching among them in a few cycles, multithreaded processors can overlap computation with memory accesses and reduce processor idle time. This paper presents an analytical performance model for multithreaded processors
Area-Performance Trade-Offs . . .
"... ... and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and performance. The basic premise of these architectures is that larger, higher-performance implementations can be constructed by replicating the basic tile across the chip. This ..."
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. This paper explores the area-performance trade-offs when designing one such tiled architecture, WaveScalar. We use a synthesizable RTL model and cycle-level simulator to perform an area/performance pareto analysis of over 200 WaveScalar processor designs ranging in size from 19mm 2 to 378mm 2 and having a 22
Performance Trade-Off in . . .
, 2006
"... The report is a detailed study of three main adders which are Ripple Carry Adder (RCA), Carry Select Adder (CSA), and Carry Look Ahead Adder (CLA). We implement all these adder in verilog and verify the result using ModelSim. Then we synthesized all three adders using Synopsys and analyze the circui ..."
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the circuits in terms of performance, area and power using design optimization. All the input and output constraints are the same for the analysis of all three circuits, and we verify that the circuit after optimization is the desired circuit as we have intended to build before optimization.
Performance Tradeoffs in Multithreaded Processors
"... 1 Introduction As we build larger and larger parallel machines, the proportion of processor time actually spent in useful work keeps diminishing. There are several reasons for the decreasing processor utilization. First, the cost of each memory access increases because network delays increase with s ..."
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1 Introduction As we build larger and larger parallel machines, the proportion of processor time actually spent in useful work keeps diminishing. There are several reasons for the decreasing processor utilization. First, the cost of each memory access increases because network delays increase with system size. Higher processor clock rates will only magnify this effect. Second, as we strive for greater speed-ups in applications through fine-grain parallelism, the number of network transactions and synchronization delays also increases.
Performance tradeoffs in read-optimized databases
- In VLDB 2006: Proceedings of the 32nd international conference on Very large data bases
, 2006
"... Database systems have traditionally optimized performance for write-intensive workloads. Recently, there has been renewed interest in architectures that optimize read performance by using column-oriented data representation and light-weight compression. This previous work has shown that under certai ..."
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Cited by 58 (14 self)
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the distinctive components of a read-optimized DBMS and describe our implementation of a high-performance query engine that can operate on both row and column-oriented data. We then use our prototype to perform an in-depth analysis of the tradeoffs between column and row-oriented architectures. We explore
Complexity/Performance Tradeoffs with Non-Blocking Loads
, 1994
"... Non-blocking loads are a very effective technique for tolerating the cache-miss latency on data cache references. We describe several methods for implementing non-blocking loads. A range of resulting hardware complexity/performance tradeoffs are investigated using an object-code translation and inst ..."
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Cited by 89 (9 self)
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Non-blocking loads are a very effective technique for tolerating the cache-miss latency on data cache references. We describe several methods for implementing non-blocking loads. A range of resulting hardware complexity/performance tradeoffs are investigated using an object-code translation
Unicast Routing: Cost-Performance Tradeoffs
, 2002
"... The objective of unicast routing is to find a path from a source to a destination. Conventional routing has been used mainly to provide connectivity. It lacks the ability to provide any kind of service guarantees and smart usage of network resources. Improving performance is possible by being aware ..."
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Cited by 1 (0 self)
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, this usually comes at the cost of increased complexity and decreased scalability. In this paper, we discuss such cost-performance tradeoffs by surveying proposed heuristic solutions and hybrid approaches.
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