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Vogels, U-Net: a user-level network interface for parallel and distributed computing, in:

by Anindya Basu , Vineet Buch , Werner Vogels , Thorsten Von Eicken - Proceedings of the 15th ACM Symposium on Operating System Principles, ACM, , 1995
"... Abstract The U-Net communication architecture provides processes with a virtual view of a network device to enable user-level access to high-speed communication devices. The architecture, implemented on standard workstations using off-the-shelf ATM communication hardware, removes the kernel from th ..."
Abstract - Cited by 597 (17 self) - Add to MetaCart
the communication path, while still providing full protection. The model presented by U-Net allows for the construction of protocols at user level whose performance is only limited by the capabilities of network. The architecture is extremely flexible in the sense that traditional protocols like TCP and UDP

Data Mining: Concepts and Techniques

by Jiawei Han, Micheline Kamber , 2000
"... Our capabilities of both generating and collecting data have been increasing rapidly in the last several decades. Contributing factors include the widespread use of bar codes for most commercial products, the computerization of many business, scientific and government transactions and managements, a ..."
Abstract - Cited by 3142 (23 self) - Add to MetaCart
retrieval, high performance computing, and data visualization. We present the material in

POWER3: Next Generation 64-bit PowerPC Processor Design Authors

by Mark Papermaster Robert, Robert Dinkjian, Michael Mayfield, Peter Lenk, Bill Ciarfella
"... IBM's new POWER3 microprocessor integrates the high-bandwidth and floating point capabilities of its POWER2 architecture predecessor into a fully scaleable 64-bit PowerPC* symmetric multi-processor (SMP) implementation. Based on PowerPC Architecture*, this microprocessor contains the fundamenta ..."
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microarchitecture, silicon technology, packaging technology, and systems architecture can be leveraged to produce outstanding high-performance computational capabilities. What follows is a description of the processor design point, the execution core, and key features - such as hardware prefetch - to reduce latency

A model for types and levels of human interaction with automation

by Raja Parasuraman, Thomas B. Sheridan, Christopher D. Wickens - IEEE Transactions on Systems Man and Cybernetics – Part A: Systems and Humans
"... Abstract—Technical developments in computer hardware and software now make it possible to introduce automation into virtually all aspects of human-machine systems. Given these technical capabilities, which system functions should be automated and to what extent? We outline a model for types and leve ..."
Abstract - Cited by 401 (26 self) - Add to MetaCart
Abstract—Technical developments in computer hardware and software now make it possible to introduce automation into virtually all aspects of human-machine systems. Given these technical capabilities, which system functions should be automated and to what extent? We outline a model for types

High performance messaging on workstations: Illinois Fast Messages (FM) for Myrinet

by Scott Pakin, Mario Lauria, Andrew Chien - In Supercomputing , 1995
"... In most computer systems, software overhead dominates the cost of messaging, reducing delivered performance, especially for short messages. Efficient software messaging layers are needed to deliver the hardware performance to the application level and to support tightly-coupled workstation clusters. ..."
Abstract - Cited by 311 (15 self) - Add to MetaCart
of the input/output (I/O) bus, and buffer management. To achieve high performance, messaging layers should assign as much functionality as possible to the host. If the network interface has DMA capability, the I/O bus should be used asymmetrically, with

Proof of a Fundamental Result in Self-Similar Traffic Modeling

by Murad S. Taqqu , Walter Willinger, Robert Sherman - COMPUTER COMMUNICATION REVIEW , 1997
"... We state and prove the following key mathematical result in self-similar traffic modeling: the superposition of many ON/OFF sources (also known as packet trains) with strictly alternating ON- and OFF-periods and whose ON-periods or OFF-periods exhibit the Noah Effect (i.e., have high variability or ..."
Abstract - Cited by 290 (8 self) - Add to MetaCart
-similarity). This provides a simple physical explanation for the presence of self-similar traffic patterns in modern high-speed network traffic that is consistent with traffic measurements at the source level. We illustrate how this mathematical result can be combined with modern high-performance computing capabilities

High-Performance

by Scinet Testbed For
"... Once each year, leading experts in ultra-high-performance networking and computing spend a week building the world’s fastest network and running applications that stress its capabilities. The rapidly increasing availability of highperformance networking is arguably computing’s most significant contr ..."
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Once each year, leading experts in ultra-high-performance networking and computing spend a week building the world’s fastest network and running applications that stress its capabilities. The rapidly increasing availability of highperformance networking is arguably computing’s most significant

Homomorphic factorization of brdfs for high-performance rendering

by Michael D. Mccool, Jason Ang, Anis Ahmad , 2001
"... Figure 1: A model rendered at real-time rates (approximately half the performance of the standard per-vertex lighting model on an NVIDIA GeForce 3) with several BRDFs approximated using the technique in this paper. From left to right: satin (anisotropic Poulin-Fournier model), krylon blue, garnet re ..."
Abstract - Cited by 101 (7 self) - Add to MetaCart
BRDFs using the available texture-mapping and computational capabilities of an accelerated graphics pipeline. We present a numerical technique, homomorphic factorization, that can decompose arbitrary BRDFs into products of two or more factors of lower dimensionality, each factor dependent on a different

High-Performance Computing

by Daniel Chavarría-mir, Andrés Márquez, Jarek Nieplocha, Kristyn Maschhoff
"... This paper describes our early experiences with a preproduction Cray XMT system that implements a scalable shared memory architecture with hardware support for multithreading. Unlike its predecessor, the Cray MTA-2 that had very limited I/O capability, the Cray XMT offers Lustre, a scalable high-per ..."
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This paper describes our early experiences with a preproduction Cray XMT system that implements a scalable shared memory architecture with hardware support for multithreading. Unlike its predecessor, the Cray MTA-2 that had very limited I/O capability, the Cray XMT offers Lustre, a scalable high-performance

The Akamai network: A platform for high-performance Internet applications

by Erik Nygren, Ramesh K. Sitaraman, Jennifer Sun - SIGOPS Oper. Syst. Rev , 2010
"... Comprising more than 61,000 servers located across nearly 1,000 networks in 70 countries worldwide, the Akamai platform delivers hundreds of billions of Internet interactions daily, helping thousands of enterprises boost the performance and reliability of their Internet applications. In this paper, ..."
Abstract - Cited by 114 (15 self) - Add to MetaCart
, we give an overview of the components and capabilities of this large-scale distributed computing platform, and offer some insight into its architecture, design principles, operation, and management.
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