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528
UPPAAL in a Nutshell
, 1997
"... . This paper presents the overall structure, the design criteria, and the main features of the tool box Uppaal. It gives a detailed user guide which describes how to use the various tools of Uppaal version 2.02 to construct abstract models of a realtime system, to simulate its dynamical behavior, ..."
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Cited by 662 (51 self)
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and verification of realtime systems, based on constraintsolving and onthefly techniques, developed jointly by Uppsala University and Aalborg University. It is appropriate for systems that can be modeled as a collection of nondeterministic processes with finite control structure and realvalued clocks
ValueBased Clock Gating and Operation Packing: Dynamic Strategies for Improving Processor Power and Performance
 ACM Transactions on Computer Systems
, 2000
"... This article presents our observations demonstrating that operations on "narrowwidth" quantities are common not only in multimedia codes, but also in more general workloads. In fact, across the SPECint95 benchmarks, over half the integer operation executions require 16 bits or less. Based ..."
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Cited by 31 (0 self)
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. Based on this data, we propose two hardware mechanisms that dynamically recognize and capitalize on these narrowwidth operations. The first, poweroriented optimization reduces processor power consumption by using operandvaluebased clock gating to turn off portions of arithmetic units
Razor: A lowpower pipeline based on circuitlevel timing speculation
 in Proc. IEEE/ACM Int. Symp. Microarchitect
, 2003
"... With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systemsonchip. One of the more effective and widely used methods for poweraware computing is dynamic voltage scaling (DVS). In order to obtain the ..."
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Cited by 288 (8 self)
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the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flipflop is introduced that doublesamples pipeline stage values, once with a fast clock and again with a time
Bayesian inference on phylogeny and its impact on evolutionary biology.
 Science
, 2001
"... 1 As a discipline, phylogenetics is becoming transformed by a flood of molecular data. These data allow broad questions to be asked about the history of life, but also present difficult statistical and computational problems. Bayesian inference of phylogeny brings a new perspective to a number of o ..."
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Cited by 235 (10 self)
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is based on a quantity called the posterior probability of a tree (where the vertical bar should be read as "given") is used to combine the prior probability of a phylogeny (Pr[Tree]) with the likelihood (Pr[Data Խ Tree]) to produce a posterior probability distribution on trees (Pr[Tree Խ Data
Understanding Protocols for Byzantine Clock Synchronization
, 1987
"... All published faulttolerant clock synchronization protocols are shown to result from refining a single paradigm. This allows the differera clock synchronization protocols to be compared and permits presemation of a single correctness analysis that holds for all. The paradigm is based on a reliab ..."
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Cited by 79 (0 self)
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All published faulttolerant clock synchronization protocols are shown to result from refining a single paradigm. This allows the differera clock synchronization protocols to be compared and permits presemation of a single correctness analysis that holds for all. The paradigm is based on a
Reducing the Number of Clock Variables of Timed Automata
 Proc. RTSS'96, 7381, IEEE
, 1996
"... We propose a method for reducing the number of clocks of a timed automaton by combining two algorithms. The first one consists in detecting active clocks, that is, those clocks whose values are relevant for the evolution of the system. The second one detects sets of clocks that are always equal. We ..."
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Cited by 77 (7 self)
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We propose a method for reducing the number of clocks of a timed automaton by combining two algorithms. The first one consists in detecting active clocks, that is, those clocks whose values are relevant for the evolution of the system. The second one detects sets of clocks that are always equal. We
Gradient Clock Synchronization
, 2004
"... We introduce the distributed gradient clock synchronization problem. As in traditional distributed clock synchronization, we consider a network of nodes equipped with hardware clocks with bounded drift. Nodes compute logical clock values based on their hardware clocks and message exchanges, and the ..."
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Cited by 40 (1 self)
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We introduce the distributed gradient clock synchronization problem. As in traditional distributed clock synchronization, we consider a network of nodes equipped with hardware clocks with bounded drift. Nodes compute logical clock values based on their hardware clocks and message exchanges
Clock Difference Diagrams
 Nordic Journal of Computing
, 1999
"... We sketch a BDDlike structure for representing unions of simple convex polyhedra, describing the legal values of a set of clocks given bounds on the values of clocks and clock differences. 1 Introduction The basic problem we are trying to tackle is the combination BDD's and DBM's (differ ..."
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Cited by 26 (8 self)
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We sketch a BDDlike structure for representing unions of simple convex polyhedra, describing the legal values of a set of clocks given bounds on the values of clocks and clock differences. 1 Introduction The basic problem we are trying to tackle is the combination BDD's and DBM
A Paradigm for Reliable Clock Synchronization
 In Proceedings Advanced Seminar of Local Area Networks
, 1986
"... Existing faulttolerant clock synchronization protocols are shown to result from refining a single clock synchronization paradigm. In that paradigm, a reliable time source periodically issues messages that cause processors to resynchronize their clocks. The reliable time source is approximated by ..."
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Cited by 38 (2 self)
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by reading all clocks in the system and using a convergence function to compute a faulttolerant average of the values read. The performance of a clock synchronization algorithm based on the paradigm can be quantified in terms of the two parameters that characterize the behavior of the convergence
SelfStabilizing Clock Synchronization in the presence of Byzantine faults
 Journal of the ACM
, 1995
"... We initiate a study of bounded clock synchronization under a more severe fault model than that proposed by Lamport and MelliarSmith [LM85]. Realistic aspects of the problem of synchronizing clocks in the presence of faults are considered. One aspect is that clock synchronization is an ongoing tas ..."
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Cited by 58 (11 self)
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. Another aspect is that the clock value is bounded. A single transient fault may cause the clock to reach the upper bound. Therefore we suggest a bounded clock that wraps around when appropriate. We present two randomized selfstabilizing protocols for synchronizing bounded clocks in the presence
Results 1  10
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528