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Long Short-term Memory

by Sepp Hochreiter, Jürgen Schmidhuber , 1995
"... "Recurrent backprop" for learning to store information over extended time intervals takes too long. The main reason is insufficient, decaying error back flow. We briefly review Hochreiter's 1991 analysis of this problem. Then we overcome it by introducing a novel, efficient method c ..."
Abstract - Cited by 454 (58 self) - Add to MetaCart
called "Long Short Term Memory" (LSTM). LSTM can learn to bridge minimal time lags in excess of 1000 time steps by enforcing constant error flow through internal states of special units. Multiplicative gate units learn to open and close access to constant error flow. LSTM's update

When are multiple gate errors significant in logic circuits

by Smita Krishnaswamy, Igor L. Markov, John P. Hayes - In Proceedings of the 2nd Workshop on System effects of Logic Soft Errors (SESLE-2 , 2006
"... Most recent works on soft errors only address circuit reliability under single gate errors caused by SEUs. In this paper, we compare the probabilities of single and multiple errors. We formulate a criterion based on gate error probabilities for considering multiple gate errors in circuit reliability ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
Most recent works on soft errors only address circuit reliability under single gate errors caused by SEUs. In this paper, we compare the probabilities of single and multiple errors. We formulate a criterion based on gate error probabilities for considering multiple gate errors in circuit

Body thickness dependence of Impact Ionization in a Multiple-Gate FinFET

by Jin-woo Han, Jiye Lee, Donggun Park, Yang-kyu Choi - IEEE EDL Vol.28, No.7 , 2007
"... Abstract—The body thickness dependence of impact ionization for a multiple-gate fin field-effect transistor (FinFET) is presented. It is found that the nonlocal effect and series resistance are distinct features of reduced impact ionization in the multiple-gate FinFET, and these effects become more ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
Abstract—The body thickness dependence of impact ionization for a multiple-gate fin field-effect transistor (FinFET) is presented. It is found that the nonlocal effect and series resistance are distinct features of reduced impact ionization in the multiple-gate FinFET, and these effects become more

MULTIPLE GATE FIELD-EFFECT TRANSISTORS FOR FUTURE CMOS TECHNOLOGIES

by Suhas N. Yadav
"... This is a review paper on the topic of multiple gate field effect transistors: MuGFETs, or FinFETs, as they are called. First, the motivation behind multiple gate FETs is presented. This is followed by looking at the evolution of FinFET technologies; the main flavors (variants) of Multigate FETs; an ..."
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This is a review paper on the topic of multiple gate field effect transistors: MuGFETs, or FinFETs, as they are called. First, the motivation behind multiple gate FETs is presented. This is followed by looking at the evolution of FinFET technologies; the main flavors (variants) of Multigate FETs

Interpolation of depth-3 arithmetic circuits with two multiplication gates

by Amir Shpilka - In STOC ’07: Proceedings of the thirty-ninth annual ACM symposium on Theory of computing , 2007
"... In this paper we consider the problem of constructing a small arithmetic circuit for a polynomial for which we have oracle access. Our focus is on n-variate polynomials, over a finite field F, that have depth-3 arithmetic circuits with two multiplication gates of degree d. We obtain the following re ..."
Abstract - Cited by 10 (2 self) - Add to MetaCart
In this paper we consider the problem of constructing a small arithmetic circuit for a polynomial for which we have oracle access. Our focus is on n-variate polynomials, over a finite field F, that have depth-3 arithmetic circuits with two multiplication gates of degree d. We obtain the following

OF AT-RISK STUDENTS: A MULTIPLE GATING APPROACH

by Herbert H. Severson, Ph. D, Bonnie Todis M. A, Maureen Barckley M. S, Alice Block M. A
"... Reliability and validity data on s procedure for identification of students "at risk " for exhibiting behavior disorders are presented. The Systematic Screening for Behavior Disorders instrument relies upon teacher judgment and normative criteria in three interrelated stages that cross val ..."
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Reliability and validity data on s procedure for identification of students "at risk " for exhibiting behavior disorders are presented. The Systematic Screening for Behavior Disorders instrument relies upon teacher judgment and normative criteria in three interrelated stages that cross validate the results of each other. Stage 1 has teachers rank students on both "externalizing " and "internalizing " behavioral dimensions. Stage 2 involves teacher completed rating measures on adaptive and maladaptive behavior while Stage 3 includes observation in classroom and free play settings which are used to confirm other measures. De,a are presented on a districtwide trial involving 158 classroom teachers in 16 schools. Observation data on 301 elementary grade students confirm the accuracy of this cost effective procedure in identifying children exhibiting behavior disorders. (Author) Reproductions supplied by EDRS are the best that can be made from the original document.

A Comparative Study of Carrier Transport for Overlapped and Nonoverlapped Multiple-Gate

by Soi Mosfets, Wei Lee, Student Member, Pin Su
"... Abstract—This paper provides a comparative study of car-rier transport characteristics for multiple-gate silicon-on-insulator MOSFETs with and without the nonoverlapped source/drain structure. For the overlapped devices, we observed Boltzmann law in subthreshold characteristics and phonon-limited be ..."
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Abstract—This paper provides a comparative study of car-rier transport characteristics for multiple-gate silicon-on-insulator MOSFETs with and without the nonoverlapped source/drain structure. For the overlapped devices, we observed Boltzmann law in subthreshold characteristics and phonon

Substrate Bias Effect Linked to Parasitic Series Resistance in Multiple-Gate SOI MOSFETs

by T. Rudenko, See Profile, Valeria Kilchytska, Nadine Collaert, Alexei N. Nazarov, Tamara Rudenko, Valeria Kilchytska, Nadine Collaert, Malgorzata Jurczak, Alexey Nazarov, Denis Fl, Senior Member
"... Substrate bias effect linked to parasitic series resistance in multiple-gate SOI MOSFETs ..."
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Substrate bias effect linked to parasitic series resistance in multiple-gate SOI MOSFETs

Unconditionally Secure Asynchronous Multiparty Computation with Quadratic Communication Per Multiplication Gate

by U Rangan
"... Secure multiparty computation (MPC) allows a set of n parties to securely compute an agreed function, even if up to t parties are under the control of an adversary. In this paper, we propose a new Asynchronous secure multiparty computation (AMPC) protocol that provides information theoretic security ..."
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security with n = 4t + 1, where t out of n parties can be under the influence of a Byzantine (active) adversary At having unbounded computing power. Our protocol communicates O(n 2 log |F|) bits per multiplication gate and involves a negligible error probability of 2 −Ω(κ) , where κ is the error parameter

An Assessment of Single-Electron Effects in Multiple-Gate SOI MOSFETs With 1.6-nm Gate Oxide Near Room Temperature

by Wei Lee, Student Member, Pin Su, Hou-yu Chen, Chang-yun Chang, Ke-wei Su, Sally Liu, Fu-liang Yang
"... Abstract—This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOS-FETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 me ..."
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Abstract—This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOS-FETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17
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