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McRT-STM: a High Performance Software Transactional Memory System for a Multi-Core Runtime

by Bratin Saha, Ali-reza Adl-tabatabai, Richard L. Hudson, Chi Cao Minh, Benjamin Hertzberg - In Proc. of the 11th ACM Symp. on Principles and Practice of Parallel Programming , 2006
"... Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex based synchronization). Unfortunately, lock based synchronization often leads to deadl ..."
Abstract - Cited by 241 (14 self) - Add to MetaCart
that is part of McRT, an experimental Multi-Core RunTime. The McRT-STM implementation uses a number of novel algorithms, and supports advanced features such as nested transactions with partial aborts, conditional signaling within a transaction, and object based conflict detection for C/C++ applications. The Mc

Multi-core and Linux * Kernel

by Suresh Siddha
"... Semiconductor technological advances in the recent years have led to the inclusion of multiple CPU execution cores in a single processor package. This processor architecture is known as Multi-core (MC) or Chip Multi Processing (CMP). Any application which is well optimized and scales with SMP will t ..."
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) take instant advantage of the MC architecture. MC also brings in performance optimization opportunities which will further enhance the performance. This paper captures the recent enhancements to the 2.6 Linux Kernel which better support and enhance the performance of Multi-core capable platforms. 1.

Kernels for Multi-Core CPUs

by John A. Stratton, Sam S. Stone, Wen-mei W. Hwu
"... Abstract. CUDA is a data parallel programming model that supports several key abstractions- thread blocks, hierarchical memory and barrier synchronization- for writing applications. This model has proven effective in programming GPUs. In this paper we describe a framework called MCUDA, which allows ..."
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CUDA programs to be executed efficiently on shared memory, multi-core CPUs. Our framework consists of a set of source-level compiler transformations and a runtime system for parallel execution. Preserving program semantics, the compiler transforms threaded SPMD functions into explicit loops, performs

Java and the Power of Multi-Core Processing

by Peter Bertels, Dirk Stroobandt
"... The new era of multi-core processing challenges software designers to efficiently exploit the parallelism that is now massively available. Programmers have to exchange the conventional sequential programming paradigm for parallel programming: single-threaded designs must be decomposed into dependent ..."
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The new era of multi-core processing challenges software designers to efficiently exploit the parallelism that is now massively available. Programmers have to exchange the conventional sequential programming paradigm for parallel programming: single-threaded designs must be decomposed

Software Support for Non-Numerical Computing on Multi-core

by Jerry Potter, Howard Jay Siegel - Chips,” 2007 International Conference on Parallel and Distributed Processing Technologies and Applications (PDPTA 2007 , 2007
"... Abstract- Multi-core chips present a new computing environment that can benefit from software support for non-numerical applications. Heterogeneous cores will allow efficient sophisticated multi-level parallel processing. Techniques are described that enable the association of the elements of relate ..."
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Abstract- Multi-core chips present a new computing environment that can benefit from software support for non-numerical applications. Heterogeneous cores will allow efficient sophisticated multi-level parallel processing. Techniques are described that enable the association of the elements

Multi-core Architectures and Streaming Applications

by Gerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. Van De Burgwal
"... In this paper we focus on algorithms and reconfigurable multi-core architectures for streaming digital signal processing (DSP) applications. The multi-core concept has a number of advantages: (1) depending on the requirements more or fewer cores can be switched on/off, (2) the multi-core structure f ..."
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In this paper we focus on algorithms and reconfigurable multi-core architectures for streaming digital signal processing (DSP) applications. The multi-core concept has a number of advantages: (1) depending on the requirements more or fewer cores can be switched on/off, (2) the multi-core structure

Compiler-Support for Robust Multi-core Computing ⋆

by Raimund Kirner, Stephan Herhut, Sven-bodo Scholz
"... Abstract. Embedded computing is characterised by the limited availability of computing resources. Further, embedded systems are often used in safety-critical applications with real-time constraints. Thus, the software development has to follow rigorous procedures to minimise the risk of system failu ..."
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failures. However, besides the inherent application complexities, there is also an increased technologybased complexity due to the shift to concurrent programming of multi-core systems. For such systems it is quite challenging to develop safe and resourceefficient systems. In this paper we give a plea

Multi-core Structural SVM Training

by Kai-wei Chang, Vivek Srikumar, Dan Roth
"... Abstract. Many problems in natural language processing and computer vision can be framed as structured prediction problems. Structural support vector ma-chines (SVM) is a popular approach for training structured predictors, where learning is framed as an optimization problem. Most structural SVM sol ..."
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called DEMI-DCD that extends the dual coordinate descent approach by decoupling the model update and inference phases into different threads. We take advantage of multi-core hardware to parallelize learning with minimal synchronization between the model update and the inference phases. We prove that our

MCSTL: The Multi-Core Standard Template Library

by Johannes Singler, Peter S, Felix Putze, Universität Karlsruhe
"... Abstract. 1 Future gain in computing performance will not stem from increased clock rates, but from even more cores in a processor. Since automatic parallelization is still limited to easily parallelizable sections of the code, most applications will soon have to support parallelism explicitly. The ..."
Abstract - Cited by 35 (11 self) - Add to MetaCart
. The Multi-Core Standard Template Library (MCSTL) simplifies parallelization by providing efficient parallel implementations of the algorithms in the C++ Standard Template Library. Thus, simple recompilation will provide partial parallelization of applications that make consistent use of the STL. We present

Efficient Smith-Waterman on multi-core with FastFlow

by Marco Aldinucci, Massimiliano Meneghin, Massimo Torquati
"... Abstract—Shared memory multiprocessors have returned to popularity thanks to rapid spreading of commodity multi-core architectures. However, little attention has been paid to supporting effective streaming applications on these architectures. In this paper we describe FastFlow, a low-level programmi ..."
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Abstract—Shared memory multiprocessors have returned to popularity thanks to rapid spreading of commodity multi-core architectures. However, little attention has been paid to supporting effective streaming applications on these architectures. In this paper we describe FastFlow, a low
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