Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network

ABSTRACT — Emerging RF systems which incorporate active phased array antenna subsystems demand major improvements in the microwave packaging and antenna interconnect technology used for the transmit/receive (T/R) modules. For active phased arrays to be viable, T/R module designs will need

of an interconnection of hundreds to thousands of 50K-100K gate IP (Intellectual Property) blocks. We assume that today's design, placement, routing, and interconnect optimization methods can handle intra-block problems, and the main issue to address is inter-module interconnection. Our work culminates

, module interconnection, simulation, and programming languages on the other. This paper attempts to provide an answer to these questions. It motivates and presents a definition and a classification framework for ADLs. The utility of the definition is demonstrated by using it to differentiate ADLs from

accessibility, scope of definition, external name,

and thus reuse is to employ interconnection languages to describe OO architectures. In this paper we present a decoupling paradigm for individual classes or class collections that facilitates reuse, introducing interconnection features at the design and programming levels. We give examples in a new, second

and maintenance system that p rov ides a control l ing environment o insure the cons is tency of a so f tware system at the module in terconnect ion leve l. It assists the programmers w i th two fac i l i t ies: In ter face control and version cont ro l. In ter face control estal) l ishes consistent in ter faces

This User Datagram Protocol (UDP) is defined to make available a datagram mode of packet-switched computer communication in the environment of an interconnected set of computer networks. This

the addition of a Module Interconnection Language to enable SARA to deal with the algorithm structure. An example illustrates how this combination can assist in the software design process.

Scalable shared-memory multiprocessors distribute memory among the processors and use scalable interconnection networks to provide high bandwidth and low latency communication. In addition, memory accesses are cached, buffered, and pipelined to bridge the gap between the slow shared memory