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587
Microprocessor Pipeline Energy Analysis
, 2003
"... The increase in high-performance microprocessor power consumption is due in part to the large power overhead of wideissue, highly speculative cores. Microarchitectural speculation, such as branch prediction, increases instruction throughput but carries a power burden due to wasted power for mis-spe ..."
Abstract
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Cited by 15 (4 self)
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instructions account for approximately 6 % of total energy, while over-provisioning imposes a tax of 17 % on average. These results suggest opportunities for power savings and energy efficiency throughout microprocessor pipelines.
Balancing Hardware Intensity in Microprocessor Pipelines
, 2003
"... The evaluation of architectural tradeoffs is complicated by implications in the circuit domain which are typically not captured in the analysis but substantially affect the results. We propose a metric of hardware intensity, which is useful for evaluating issues that affect both circuits and archite ..."
Abstract
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Cited by 22 (1 self)
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and power, assuming the optimal tuning of the pipeline. These relations will guide the architect to achieve an energy-optimal balance between architectural complexity and hardware intensity.
Ultra low-cost defect protection for microprocessor pipelines
- In Proceedings of the 12th International conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS
, 2006
"... The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the ..."
Abstract
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Cited by 40 (8 self)
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the yield and product lifetime of future systems. In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects. To achieve this goal we combine area-frugal on-line testing techniques and system
Automatic Verification of Pipelined Microprocessor Control
, 1994
"... We describe a technique for verifying the control logic of pipelined microprocessors. It handles more complicated designs, and requires less human intervention, than existing methods. The technique automaticMly compares a pipelined implementation to an architectural description. The CPU time nee ..."
Abstract
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Cited by 290 (7 self)
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We describe a technique for verifying the control logic of pipelined microprocessors. It handles more complicated designs, and requires less human intervention, than existing methods. The technique automaticMly compares a pipelined implementation to an architectural description. The CPU time
FFTW: An Adaptive Software Architecture For The FFT
, 1998
"... FFT literature has been mostly concerned with minimizing the number of floating-point operations performed by an algorithm. Unfortunately, on present-day microprocessors this measure is far less important than it used to be, and interactions with the processor pipeline and the memory hierarchy have ..."
Abstract
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Cited by 602 (4 self)
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FFT literature has been mostly concerned with minimizing the number of floating-point operations performed by an algorithm. Unfortunately, on present-day microprocessors this measure is far less important than it used to be, and interactions with the processor pipeline and the memory hierarchy have
Energy Dissipation in General Purpose Microprocessors
- IEEE Journal of Solid-state Circuits
, 1996
"... Abstract-In this paper we investigate possible ways to improve the energy efficiency of a general purpose microprocessor. We show that the energy of a processor depends on its performance, so we chose the energy-delay product to compare different processors. To improve the energy-delay product we e ..."
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Cited by 260 (1 self)
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Abstract-In this paper we investigate possible ways to improve the energy efficiency of a general purpose microprocessor. We show that the energy of a processor depends on its performance, so we chose the energy-delay product to compare different processors. To improve the energy-delay product we
Pipeline gating: speculation control for energy reduction
- In Proceedings of the 25th Annual International Symposium on Computer Architecture
, 1998
"... Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although speculative execution is essential for increasing the instructions per cycle (IPC), it does come at a cost. A large amount o ..."
Abstract
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Cited by 288 (3 self)
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Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although speculative execution is essential for increasing the instructions per cycle (IPC), it does come at a cost. A large amount
The optimum pipeline depth for a microprocessor
- In Proc. of the 29th Intl. Symp. on
, 2002
"... hart @ watson, ibm. corn trpuzak @ us. ibrn.com The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing architectural parameters affect the optimal pipeline length: the degree of ..."
Abstract
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Cited by 89 (3 self)
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hart @ watson, ibm. corn trpuzak @ us. ibrn.com The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing architectural parameters affect the optimal pipeline length: the degree
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design
- In Proc. 32nd Annual Intl. Symp. on Microarchitecture
, 1999
"... Building a high-petformance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. To&rther complicate this task, deep submicro ..."
Abstract
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Cited by 374 (15 self)
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of correctness in microprocessor designs. The approach works by augmenting the commit phase of the processor pipeline with a functional checker unit. Thefunctional checker verifies the correctness of the core processor’s computation, only permitting correct results to commit. Overall design cost can
Verifying Pipelined Microprocessors
- In Proceedings of the 1995 IFIP Conference on Hardware Description Languages and their Applications (CHDL
, 1995
"... Recently there has been much research in verifying pipelined microprocessors. Even so, there has been little consensus on what form the correctness statement should take. Put another way, what should we be verifying about pipelined microprocessors? We believe that the correctness statement should ..."
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Cited by 12 (0 self)
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Recently there has been much research in verifying pipelined microprocessors. Even so, there has been little consensus on what form the correctness statement should take. Put another way, what should we be verifying about pipelined microprocessors? We believe that the correctness statement
Results 1 - 10
of
587
