Results 1 - 10 of 365

SEA: Fast power estimation for micro-architectures

by Praveen Kalla, Jörg Henkel, Xiaobo Sharon Hu
"... Abstract — Various approaches for micro-architectural power/ energy estimation have been introduced, mainly driven by the need to obtain fast power/energy estimates during early phases of complex SOC designs. In contrast to previous approaches we study power/energy estimation for highly optimized sy ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
in the SEA framework that estimates energy/power consumed by a software program, taking specific micro-architectural features of the underlying programmable hardware core into consideration. With this high accuracy in energy estimation we achieve around 5 orders of magnitude faster estimations compared

Automated Micro-architectural Test Generation for Validation of Modern Processors

by Heon-mo Koo, Prabhat Mishra
"... Abstract — Design complexity of todays microprocessors is in-creasing at an alarming rate to cope up with the required perfor-mance improvement by adopting complicated micro-architectural features such as deep pipelines, dynamic scheduling, out-of-order and superscalar execution, and dynamic specula ..."
Abstract - Add to MetaCart
Abstract — Design complexity of todays microprocessors is in-creasing at an alarming rate to cope up with the required perfor-mance improvement by adopting complicated micro-architectural features such as deep pipelines, dynamic scheduling, out-of-order and superscalar execution, and dynamic

A retargetable micro-architecture simulator

by Wai Sum Mong , Jianwen Zhu - In Proceedings of the 40th conference on Design automation , 2003
"... ABSTRACT The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) simulators have been reported, the more relevant micro-architecture simulators, which are capable of modeling the ..."
Abstract - Cited by 7 (0 self) - Add to MetaCart
the detailed machine features such as cache organization, branch prediction and out-of-order scheduler, have not be equipped with retargetability. In this paper, we propose a new methodology that can generate completed micro-architecture simulators from the abstract ISA and the application binary interface

A fast and flexible performance simulator for microarchitecture trade-off analysis on UltraSPARC

by Marc Tremblay, Guillermo Maturana, Atsushi Inoue, Les Kohn - Proc. 32st ACM/IEEE Des. Auto Conf , 1995
"... Abstract- Over one hundred micro-architecture features were analyzed and simulated in order to determine if they should be included in UltraSPARC-I. A fast and flexible performance sim-ulator was developed in order to model these features. In this paper, we describe UPS (UltraSPARC-I Performance Sim ..."
Abstract - Cited by 4 (0 self) - Add to MetaCart
Abstract- Over one hundred micro-architecture features were analyzed and simulated in order to determine if they should be included in UltraSPARC-I. A fast and flexible performance sim-ulator was developed in order to model these features. In this paper, we describe UPS (UltraSPARC-I Performance

A Framework to Model Branch Prediction for Worst Case Execution Time Analysis

by Tulika Mitra, Abhik Roychoudhury
"... Estimating the Worst Case Execution Time (WCET) of a program on a given hardware platform is useful in the design of embedded real-time systems. These systems communicate with the external environment in a timely fashion, and thus impose constraints on the execution time of programs. Estimating the ..."
Abstract - Cited by 3 (0 self) - Add to MetaCart
the WCET of a program ensures that these constraints are met. WCET analysis schemes typically model micro-architectural features in modern processors, such as pipeline and caches, to obtain tight estimates. In this paper,

From Machine Scheduling to VLIW Instruction Scheduling

by Benot Dupont De Dinechin
"... ... and instruction scheduling problems on modern VLIW processors such as the STMicroelectronics ST200. Our motivations are to apply the machine scheduling techniques that are relevant to instruction scheduling in VLIW compilers, and to understand how processor micro-architecture features impact ..."
Abstract - Cited by 3 (0 self) - Add to MetaCart
... and instruction scheduling problems on modern VLIW processors such as the STMicroelectronics ST200. Our motivations are to apply the machine scheduling techniques that are relevant to instruction scheduling in VLIW compilers, and to understand how processor micro-architecture features impact

A Flexible Simulator of Pipelined Processors

by Ben Juurlink , Koen Bertels, Bei Li
"... A flexible, parameterizable simulator of pipelined processors is presented. The simulator allows to configure several (micro-)architectural features such as the pipeline depth, the stage in which branch execution occurs, whether or not register file forwarding is performed, and the number of bran ..."
Abstract - Add to MetaCart
A flexible, parameterizable simulator of pipelined processors is presented. The simulator allows to configure several (micro-)architectural features such as the pipeline depth, the stage in which branch execution occurs, whether or not register file forwarding is performed, and the number

Loop Level Analysis of Security and Network Applications

by Dinesh C Suresh, Satya R. Mohanty, Walid A. Najjar, Laxmi N. Bhuyan, Frank Vahid
"... Abstract--It has been known that loops constitute the most executed segments of programs and therefore are the best candidates for hardware implementation. We present a set of profiling tools that are specifically dedicated to loop profiling and do support combined function and loop profiling. One t ..."
Abstract - Cited by 3 (0 self) - Add to MetaCart
tool relies on an instruction set simulator and can therefore be augmented with architecture and micro-architecture features simulation while the other is based on compile-time instrumentation of gcc and therefore has no slow down compared to the original program Index Terms—Loop analysis, profiling

Precise Micro-architectural Modeling for WCET Analysis via AI+SAT

by Abhijeet Banerjee, Sudipta Chattopadhyay, Abhik Roychoudhury
"... Abstract—Hard real-time systems are required to meet critical deadlines. Worst case execution time (WCET) is therefore an important metric for the system level schedulability analysis of hard real-time systems. However, performance enhancing features of a processor (e.g. pipeline, caches) makes WCET ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
WCET analysis a very difficult problem. In this paper, we propose a novel approach to combine abstract interpretation (AI) and satisfiability (SAT) checking (hence the name AI+SAT) for different varieties of micro-architectural modeling. Our work in this paper is inspired by the research advances

Profiling tools for hardware/software partitioning of embedded applications

by Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt - ACM SIGPLAN Notices
"... Loops constitute the most executed segments of programs and therefore are the best candidates for hardware software partitioning. We present a set of profiling tools that are specifically dedicated to loop profiling and do support combined function and loop profiling. One tool relies on an instructi ..."
Abstract - Cited by 22 (2 self) - Add to MetaCart
on an instruction set simulator and can therefore be augmented with architecture and micro-architecture features simulation while the other is based on compile-time instrumentation of gcc and therefore has very little slow down compared to the original program We use the results of the profiling to identify
Results 1 - 10 of 365