programs (with a median of 5 l%), and the overall execution time reduction ranges from 2 % to 23 % (with a median of 7%) on a 333 MHz PowerPC workstation with 128 MB memory. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided

compiled code size by 25%. This algorithm is very fast: it analyzes 3300 source lines per second on an 80 MHz Pow-erPC 601. Because of its accuracy and speed, this algorithm is an excellent candidate for inclusion in production C++ compilers. 1

This paper presents an extensive and careful study of the software implementation on workstations of the NIST-recommended elliptic curves over binary fields. We also present the results of our implementation in C on a Pentium II 400 MHz workstation.

The development of a PowerPC TM fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described. Detailed architectural studies led to a design which maximizes performance in a small transistor count implementation. Manufactured in Motorola’s 0.5−µm Complementary

The development of a PowerPC fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described. Detailed architectural studies led to a design which maximizes performance in a small transistor count implementa- tion. Manufactured in Motorola's 0.5-m

Abstract — Single-event upset effects from heavy ions were measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes at three frequencies of 500, 1066 and 1600 MHz. Frequency dependence of single-event upsets is discussed. The results of our studies suggest the single

, and (3) the Process Network model of computation. We find that it is feasible for a 4-GFLOP digital interpolation process network beamformer to run in real-time on a Sun workstation with 16 UltraSPARC-II processors running at 336 MHz. The workstation beamformer significantly reduces cost and development

A 550MHz 64b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS [1]. Both the design and the associated CAD methodology (point tools, flow, and models) were modified to handle demands specific

Sun Microsystems recently announced a new line of high-performance Sun FireTM Midframe servers and Sun BladeTM 1000 workstations based on 750-MHz UltraSPARC-III microprocessors. These new computers offer exceptional performance for numerically intensive MCAE applications at reasonable prices

The key to efficient parallel computing on workstations clusters is a communication subsystem that removes the operating system from the communication path and eliminates all unnecessary protocol overhead. At the same time, protection and a stable multi-user, multiprogrammed environment cannot