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multithreading for memory intensive applications
"... Exploring the performance limits of simultaneous ..."
Synthesis of heterogeneous distributed architectures for memory-intensive applications
- in Proc. Int. Conf. Computer-Aided Design
, 2003
"... Abstract — Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latencies, etc. The high potential of single-chip distributed logicmemory architectures in addressing many of these iss ..."
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Cited by 5 (1 self)
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Abstract — Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latencies, etc. The high potential of single-chip distributed logicmemory architectures in addressing many
High-Level Synthesis of Control and Memory Intensive Applications
, 2000
"... Recent developments in microelectronic technology and CAD technology allow production of larger and larger integrated circuits in shorter and shorter design times. At the same time, the abstraction level of specifications is getting higher both to cover the increased complexity of systems more effic ..."
Abstract
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Cited by 11 (2 self)
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efficiently and to make the design process less error prone. Although High-Level Synthesis (HLS) has been successfully used in many cases, it is still not as indispensable today as layout or logic synthesis. Various application specific synthesis strategies have been developed to cope with the problems
Genome-scale computational approaches to memory-intensive applications in systems biology
- In Proceedings, Supercomputing
, 2005
"... Graph-theoretical approaches to biological network analysis have proven to be effective for small networks but are computationally infeasible for comprehensive genome-scale systems-level elucidation of these networks. The difficulty lies in the NP-hard nature of many global systems biology problems ..."
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Cited by 15 (6 self)
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that, in practice, translates to exponential (or worse) run times for finding exact optimal solutions. Moreover, these problems, especially those of an enumerative flavor, are often memory-intensive and must share very large sets of data effectively across many processors. For example, the enumeration
Optimized pre-copy live migration for memory intensive applications
- In SC ’11: 24th International Conference for High Performance Computing, Networking, Storage and Analysis
, 2011
"... Abstract—Live migration is a widely used technique for resource consolidation and fault tolerance. KVM and Xen use iterative pre-copy approaches which work well in practice for commercial applications. In this paper, we study pre-copy live migration of MPI and OpenMP scientific applications running ..."
Abstract
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Cited by 5 (0 self)
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on KVM and present a detailed performance analysis of the migration process. We show that due to a high rate of memory changes, the current KVM rate control and target downtime heuristics do not cope well with HPC applications: statically choosing rate limits and downtimes is infeasible and current
A FEEDBACK CONTROL MECHANISM FOR BALANCING I/O- AND MEMORY-INTENSIVE APPLICATIONS ON CLUSTERS ∗
"... Abstract. One common assumption of existing models of load balancing is that the weights of resources and I/O buffer size are statically configured and cannot be adjusted based on a dynamic workload. Though the static configuration of these parameters performs well in a cluster where the workload ca ..."
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indicate the significance of the resources, and (2) minimizing the number of page faults for memory-intensive jobs while increasing the utilization of the I/O buffers for I/O-intensive jobs by manipulating the I/O buffer size. Results from extensive tracedriven simulation experiments show that compared
Data Cache Sizing for Embedded Processor Applications
, 1997
"... We present a technique for determining the best data cache size required for a given memory-intensive application. ..."
Abstract
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Cited by 18 (4 self)
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We present a technique for determining the best data cache size required for a given memory-intensive application.
Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines
- PROC. INTL. PARALLEL AND DISTRIBUTED PROCESSING SYMP. (IPDPS
, 2002
"... The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive benchmarks to evaluate a mixed logic and DRAM processor called VIRAM as a building block for scientific computing. For ea ..."
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Cited by 4 (0 self)
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The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive benchmarks to evaluate a mixed logic and DRAM processor called VIRAM as a building block for scientific computing
Paravirtualization effect on single- and multi-threaded memory-intensive linear algebra software
, 2008
"... Previous studies have revealed that paravirtualization imposes minimal performance overhead on High Performance Computing (HPC) workloads, while exposing numerous benefits for this field. In this study, we are investigating the impact of paravirtualization on the performance of automatically-tuned s ..."
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Cited by 3 (0 self)
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. Furthermore, we show that it is possible to achieve memory sharing among OS instances at native speeds. These results expose new benefits to memory-intensive applications arising from the ability to slim down the guest OS without influencing the system performance. In addition, our findings support a novel
Synthesis of Power-Efficient Memory-Intensive Systems-on-Chip
"... Recent commercial trends combining computer, personal communication, and commodity electronics have resulted in a new set of system design requirements focusing on power minimization and design reuse. We have developed a new modular synthesis technique for the design of core-based memory-intensive a ..."
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Recent commercial trends combining computer, personal communication, and commodity electronics have resulted in a new set of system design requirements focusing on power minimization and design reuse. We have developed a new modular synthesis technique for the design of core-based memory-intensive
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