Results 1 - 10 of 661

HwA2: SPECIAL MEMORY INTERLEAVING SCHEMES

by Montse Peiron, Mateo Valero, Eduard Ayguadé, Tomás Lang
"... The synchronized and simultaneous access to several vectors that form a single stream is typical in SIMD vector multiprocessors as well as in MIMD superscalar multiprocessors with decoupled access. In this paper we propose a block-interleaved storage scheme and an out-of-order access mechanism that ..."
Abstract - Add to MetaCart
The synchronized and simultaneous access to several vectors that form a single stream is typical in SIMD vector multiprocessors as well as in MIMD superscalar multiprocessors with decoupled access. In this paper we propose a block-interleaved storage scheme and an out-of-order access mechanism

High-performance low-memory interleaver banks for turbo-codes

by Stewart Crozier, Paul Guin - In Proc. Vehicular Tech. Conf , 2001
"... A new method of designing high-performance, low-memory, interleaver banks for Turbo-codes is presented. The new interleavers are called dithered relative prime (DRP) interleavers. Only a small number of parameters are required to both store and implement each interleaver in the bank. The error rate ..."
Abstract - Cited by 21 (1 self) - Add to MetaCart
A new method of designing high-performance, low-memory, interleaver banks for Turbo-codes is presented. The new interleavers are called dithered relative prime (DRP) interleavers. Only a small number of parameters are required to both store and implement each interleaver in the bank. The error rate

Why there are complementary learning systems in the hippocampus and neocortex: insights from the successes and failures of connectionist models of learning and memory

by James L. McClelland, Bruce L. McNaughton, Randall C. O'Reilly , 1995
"... Damage to the hippocampal system disrupts recent memory but leaves remote memory intact. The account presented here suggests that memories are first stored via synaptic changes in the hippocampal system, that these changes support reinstatement of recent memories in the neocortex, that neocortical s ..."
Abstract - Cited by 675 (39 self) - Add to MetaCart
synapses change a little on each reinstatement, and that remote memory is based on accumulated neocortical changes. Models that learn via changes to connections help explain this organization. These models discover the structure in ensembles of items if learning of each item is gradual and interleaved

Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique

by Tom Vancourt, Martin Herbordt - in Field Programmable Logic and Applications, International Conference on, 2006
"... Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA implementations of such algorithms would benefit from concurrent, non-interfering access to all points in each cluster. Wh ..."
Abstract - Cited by 2 (0 self) - Add to MetaCart
. When clusters contain dozens of points and access patterns are irregular, multiported memories are infeasible and vector-oriented approaches are inapplicable. Instead, the grid points may be distributed across multiple interleaved memory banks so that, when accessing any cluster, each point comes from

Software Interleaving

by Ricardo Bianchini , Mark E. Crovella, Leonidas Kontothanassis, Thomas J. LeBlanc - IN PROCEEDINGS OF THE 6TH SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING , 1994
"... In this paper, we investigate the costs and benefits of implementing memory interleaving in software. As our main contribution, we compare software memory interleaving to row-major allocation and logarithmic broadcasting. Our analysis demonstrates the clear superiority of software interleaving over ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
In this paper, we investigate the costs and benefits of implementing memory interleaving in software. As our main contribution, we compare software memory interleaving to row-major allocation and logarithmic broadcasting. Our analysis demonstrates the clear superiority of software interleaving over

Pseudo-Randomly Interleaved Memory

by B. Ramakrishna Rau - IN PROCEEDINGS OF THE 18TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE , 1991
"... Interleaved memories are often used to provide the high bandwidth needed by multi- processors and high performance uniprocessors. The manner in which memory locations are distributed across the memory modules has a significant influence on whether, and for which types of reference patterns, the full ..."
Abstract - Cited by 91 (0 self) - Add to MetaCart
Interleaved memories are often used to provide the high bandwidth needed by multi- processors and high performance uniprocessors. The manner in which memory locations are distributed across the memory modules has a significant influence on whether, and for which types of reference patterns

Memory access buffering in multiprocessors

by Michel Dubois, Chrlstoph Scheurich, Faye Briggs - In Proceedings of the 13th Annual International Symposium on Computer Architecture , 1986
"... In highly-pipelined machines, instructions and data are prefetched and buffered in both the processor and the cache. This is done to reduce the average memory access la-tency and to take advantage of memory interleaving. Lock-up free caches are designed to avoid processor blocking on a cache miss. W ..."
Abstract - Cited by 254 (4 self) - Add to MetaCart
In highly-pipelined machines, instructions and data are prefetched and buffered in both the processor and the cache. This is done to reduce the average memory access la-tency and to take advantage of memory interleaving. Lock-up free caches are designed to avoid processor blocking on a cache miss

Unbounded Transactional Memory

by C. Scott Ananian, Krste Asanović, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie , 2005
"... Background: Programming in a shared-memory environment often requires the use of atomic regions for program correctness. Traditionally, atomicity is achieved through critical sections protected by locks. Unfortunately, locks are very difficult to program with since they introduce problems such as de ..."
Abstract - Cited by 261 (8 self) - Add to MetaCart
on the global memory state. Two regions are atomic if, after they are run, they can viewed as having run in some serial order with no interleaved instructions. HTM ensures atomicity by simply running the atomic region speculatively. If no other processor accesses any of the same memory locations as the atomic

Co-Design of Interleaved Memory Systems

by Hua Lin, Wayne Wolf , 2000
"... Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve high efficiency for interleaved memory. In this paper, we introduce a design framework that integrates these two optimizat ..."
Abstract - Cited by 3 (0 self) - Add to MetaCart
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve high efficiency for interleaved memory. In this paper, we introduce a design framework that integrates these two

Interleaved Memory................................................................................................................................... 3

by Shyamalendu Sarkar, Durga Prasad P V, Narayanan A N
"... Cell Local Memory..................................................................................................................................... 3 ..."
Abstract - Add to MetaCart
Cell Local Memory..................................................................................................................................... 3
Results 1 - 10 of 661