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4 Microprocessor Main Memory Cache Memory
, 2009
"... – Access time is less – Power Consumption is less ..."
Cache memories
- ACM Computing Surveys
, 1982
"... Cache memories are used in modern, medium and high-speed CPUs to hold temporarily those portions of the contents of main memory which are {believed to be) currently in use. Since instructions and data in cache memories can usually be referenced in 10 to 25 percent of the time required to access main ..."
Abstract
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Cited by 688 (11 self)
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Cache memories are used in modern, medium and high-speed CPUs to hold temporarily those portions of the contents of main memory which are {believed to be) currently in use. Since instructions and data in cache memories can usually be referenced in 10 to 25 percent of the time required to access
Cost-Aware WWW Proxy Caching Algorithms
- IN PROCEEDINGS OF THE 1997 USENIX SYMPOSIUM ON INTERNET TECHNOLOGY AND SYSTEMS
, 1997
"... Web caches can not only reduce network traffic and downloading latency, but can also affect the distribution of web traffic over the network through costaware caching. This paper introduces GreedyDualSize, which incorporates locality with cost and size concerns in a simple and non-parameterized fash ..."
Abstract
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Cited by 540 (6 self)
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improve the performance of main-memory caching of Web documents.
Locality-Aware Request Distribution in Cluster-based Network Servers
, 1998
"... We consider cluster-based network servers in which a front-end directs incoming requests to one of a number of back-ends. Specifically, we consider content-based request distribution: the front-end uses the content requested, in addition to information about the load on the back-end nodes, to choose ..."
Abstract
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Cited by 327 (21 self)
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, to choose which back-end will handle this request. Content-based request distribution can improve locality in the back-ends' main memory caches, increase secondary storage scalability by partitioning the server's database, and provide the ability to employ back-end nodes that are specialized
CACHING Registers Cache MainMemory Disk
"... Cache is fast (1–5 cycle access time) memory sitting between fast registers and slow RAM (10–100 cycles access time) ..."
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Cache is fast (1–5 cycle access time) memory sitting between fast registers and slow RAM (10–100 cycles access time)
Cache-Conscious Index Structures for Main-Memory Databases
, 2004
"... access method, cache consciousness, data locality, data structure, main-memory database The recent hardware evolution has widened the speed gap between main memory and the processor. As a consequence, in many cases memory access has become the main bottle-neck even in disk-based databases. The perfo ..."
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access method, cache consciousness, data locality, data structure, main-memory database The recent hardware evolution has widened the speed gap between main memory and the processor. As a consequence, in many cases memory access has become the main bottle-neck even in disk-based databases
On Null Spaces and their Application to Model Randomisation and Interleaving in Cache Memories
, 2002
"... Cache memories bridge the growing access-time gap between the processor and the main memory. Cache memories use randomisation functions for two purposes: (i) to limit the amount of search when looking up an address in the cache and (ii) to interleave the access stream over multiple independent ba ..."
Abstract
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Cited by 3 (1 self)
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Cache memories bridge the growing access-time gap between the processor and the main memory. Cache memories use randomisation functions for two purposes: (i) to limit the amount of search when looking up an address in the cache and (ii) to interleave the access stream over multiple independent
Optimizing main-memory join on modern hardware
- IEEE Transactions on Knowledge and Data Eng
, 2002
"... AbstractÐIn the past decade, the exponential growth in commodity CPU's speed has far outpaced advances in memory latency. A second trend is that CPU performance advances are not only brought by increased clock rate, but also by increasing parallelism inside the CPU. Current database systems hav ..."
Abstract
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Cited by 64 (15 self)
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designed to optimize memory access. The performance of this algorithm is quantified using a detailed analytical model that incorporates memory access costs in terms of a limited number of parameters, such as cache sizes and miss penalties. We also present a calibration tool that extracts such parameters
Caching in the Sprite Network File System
- ACM Transactions on Computer Systems
, 1988
"... The Sprite network operating system uses large main-memory disk block caches to achieve high performance in its file system. It provides non-write-through file caching on both client and server machines. A simple cache consistency mechanism permits files to be shared by multiple clients without dang ..."
Abstract
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Cited by 296 (12 self)
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The Sprite network operating system uses large main-memory disk block caches to achieve high performance in its file system. It provides non-write-through file caching on both client and server machines. A simple cache consistency mechanism permits files to be shared by multiple clients without
Broadcast Disks: Data Management for Asymmetric Communications Environments
, 1995
"... This paper proposes the use of repetitive broadcast as a way of augmenting the memory hierarchy of clients in an asymmetric communication environment. We describe a new technique called “Broadcast Disks” for structuring the broadcast in a way that provides improved performance for non-uniformly acce ..."
Abstract
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Cited by 448 (19 self)
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-uniformly accessed data. The Broadcast Disk superimposes multiple disks spinning at different speeds on a single broadcast channel — in effect creating an arbitrarily fine-grained memory hierarchy. In addition to proposing and defining the mechanism, a main result of this work is that exploiting the potential
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