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3,556
Power-aware deterministic block allocation for low-power way-selective cache structure
"... Abstract ..."
Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power
- in Proceedings of the 28th International Symposium on Computer Architecture
, 2001
"... Power dissipation is increasingly important in CPUs ranging from those intended for mobile use, all the way up to highperformance processors for high-end servers. While the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern. Chipmakers expect tha ..."
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Cited by 280 (26 self)
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of frequent use when first brought into the cache, and then have a period of “dead time ” before they are evicted. By devising effective, low-power ways of deducing dead time, our results show that in many cases we can reduce L1 cache leakage energy by 4x in SPEC2000 applications without impacting performance
SLAC-PUB-14483 Compact, Low-power and Precision Timing Photodetector Readout
"... Photodetector readout for next generation high event rate particle identificatio and single-photon detection requires a digitizer capable of integrated recording of dense arrays of sensor elements with high analog bandwidth (precision timing) and large record depth, in a cost-effective, compact and ..."
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and low-power way. Simply stated, one cannot do better than having a high-fidelit “oscilloscope on a chip ” for every sensor channel. A firs version of the Buffered Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons learned from the development of the Large Analog Bandwidth
Low-Power Branch Prediction
"... Low-power design has gained much attention recently, especially for computing on batterypowered equipments. Reducing BTB (branch target buffer) accesses is an effective way to reduce processor power consumption, since BTB consumes a significant portion of power in a processor. In this paper, we prop ..."
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Low-power design has gained much attention recently, especially for computing on batterypowered equipments. Reducing BTB (branch target buffer) accesses is an effective way to reduce processor power consumption, since BTB consumes a significant portion of power in a processor. In this paper, we
High performance messaging on workstations: Illinois Fast Messages (FM) for Myrinet
- In Supercomputing
, 1995
"... In most computer systems, software overhead dominates the cost of messaging, reducing delivered performance, especially for short messages. Efficient software messaging layers are needed to deliver the hardware performance to the application level and to support tightly-coupled workstation clusters. ..."
Abstract
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Cited by 311 (15 self)
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. Illinois Fast Messages (FM) 1.0 is a high speed messaging layer that delivers low latency and high bandwidth for short messages. For 128-byte packets, FM achieves bandwidths of 16.2 MB/s and one-way latencies 32 s on Myrinet-connected SPARCstations (user-level to user-level). For shorter packets, we have
Low-power CMOS clock drivers
, 1995
"... The clock tree of modern synchronous VLSI circuits can consume as much as 50% of their entire power budget. Different methods of decreasing clock power dissipation have been proposed based on low-voltage swings, double-edge triggered flip-flops, gated clocks, etc. In this paper we propose two types ..."
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Cited by 6 (1 self)
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voltages (V dd and V dd=2, V dd=2 can be replaced by a tank capacitor). The second CMOS driver proposed targets dual-phase clocking schemes and achieves low-power operation by charge reuse. The proposed circuits are more than twice larger and slightly slower than standard inverter-chain clock drivers
Quantization Strategies For Low-Power Communications
, 2001
"... Power reduction in digital communication systems can be achieved in many ways. Reduction of the wordlengths used to represent data and control variables in the digital circuits comprising a communication system is an effective strategy, as register power consumption increases with wordlength. Anothe ..."
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Cited by 9 (1 self)
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Power reduction in digital communication systems can be achieved in many ways. Reduction of the wordlengths used to represent data and control variables in the digital circuits comprising a communication system is an effective strategy, as register power consumption increases with wordlength
P oS(PD07)026 Compact, Low-power and Precision Timing Photodetector Readout
, 2007
"... Photodetector readout for next generation high event rate particle identification and single-photon detection requires a digitizer capable of integrated recording of dense arrays of sensor elements with high analog bandwidth (precision timing) and large record depth, in a cost-effective, compact and ..."
Abstract
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and low-power way. Simply stated, one cannot do better than having a high-fidelity “oscilloscope on a chip ” for every sensor channel. A first version of the Buffered Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons learned from the development of the Large Analog Bandwidth
Hierarchical Bayesian Inference in the Visual Cortex
, 2002
"... this paper, we propose a Bayesian theory of hierarchical cortical computation based both on (a) the mathematical and computational ideas of computer vision and pattern the- ory and on (b) recent neurophysiological experimental evidence. We ,2 have proposed that Grenander's pattern theory 3 coul ..."
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Cited by 300 (2 self)
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could potentially model the brain as a generafive model in such a way that feedback serves to disambiguate and 'explain away' the earlier representa- tion. The Helmholtz machine 4, 5 was an excellent step towards approximating this proposal, with feedback implementing priors. Its development
Low-Power Design of Asynchronous Microprocessors
"... This paper describes the various architectures used for Low-Power asynchronous microprocessors. Based on micropipelines, some architectures contain a large number of pipeline stages while other architectures present few stages like synchronous RISC architectures. A large number of pipeline stages re ..."
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This paper describes the various architectures used for Low-Power asynchronous microprocessors. Based on micropipelines, some architectures contain a large number of pipeline stages while other architectures present few stages like synchronous RISC architectures. A large number of pipeline stages
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