Results 1 - 7 of 7

Programmable Logic Devices: A Test Approach for the Input/Output

by Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira - Blocks and Pad-to-Pin Interconnections”, 4 th IEEE Latin-American Test Workshop Digest of Papers , 2003
"... In the last few years, an increasing use of Programmable Logic Devices (PLDs) in the development of new embedded and systems-on-a-chip (SoC) solutions created the need of new test procedures for this kind of components. Several approaches, depending on the type of PLDs used, were proposed in the lit ..."
Abstract - Cited by 2 (2 self) - Add to MetaCart
in the literature, addressing the test of the configurable logic array, the interconnection arrays and the configuration memory. However, very little work has been done concerning the specific test of Input/Output Blocks (IOBs) and pad-to-pin bonds. In this paper, a method aimed at covering the test of the IOBs

Architectural Description

by Virtex V, Virtex Array , 2002
"... The Virtex user-programmable gate array, shown in Figure 1, comprises two major configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs). • CLBs provide the functional elements for constructing logic • IOBs provide the interface between the package pins and the CLBs CLB ..."
Abstract - Add to MetaCart
The Virtex user-programmable gate array, shown in Figure 1, comprises two major configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs). • CLBs provide the functional elements for constructing logic • IOBs provide the interface between the package pins and the CLBs

Thermal Testing On Programmable Logic Devices

by Sergio Lopez-Buedo Javier, Javier Garrido, Eduardo Boemo - IEEE Int’l Symp. Circuits and Systems , 1998
"... In this work, an FPGA-oriented temperature monitoring scheme is presented. A control circuit enables a ring-oscillator during a short period and measures its output frequency, a magnitude that is a function of the die temperature. Several sensors have been constructed using Xilinx chips, obtaining s ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
or the IOB clamping diodes, has also been verified. The use of ringoscillators convert the FPGAs in a powerful tool for researchers interested in thermal modeling of integrated circuits. Just the possibility of "moving" a sensor (or an array of them) over the die, in a simple, fast, and inexpensive

(RNN) and a Fuzzy Logic Controller (FLC) In Closed Loop System to Regulate Blood Glucose for Type-1 Diabetic Patients

by Fayrouz Allam, Zaki Nossair, Hesham Gomma, Ibrahim Ibrahim, Mona Abdelsalam
"... Abstract — Type-1 diabetes is a disease characterized by high blood-glucose level. Using a fully automated closed loop control system improves the quality of life for type1 diabetic patients. In this paper, a scalable closed loop blood glucose regulation system which is tuned to each patient is pres ..."
Abstract - Add to MetaCart
is presented. This control system doesn't need any data entry from the patient. A recurrent neural network (RNN) is used as a nonlinear predictor and a fuzzy logic controller (FLC) is used to determine the insulin dosage which is required to regulate the blood glucose level. The insulin infusion

An IO block array in a radiation-hardened SOI SRAM-based FPGA

by Stanley L. Chen(陈陵都
"... Abstract: We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 m partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the c ..."
Abstract - Add to MetaCart
Abstract: We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 m partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding

I DDQ Testing of Input/Output Resources of SRAM-based FPGAs

by unknown authors
"... This paper presents a quiescent current-based (IDDQ) approach for testing input/output resources in SRAM-based FPGAs. Input/output resources include input/output blocks (IOBs) and the I/O interconnect. Test generation and application strategies are proposed by taking into account the limited control ..."
Abstract - Add to MetaCart
This paper presents a quiescent current-based (IDDQ) approach for testing input/output resources in SRAM-based FPGAs. Input/output resources include input/output blocks (IOBs) and the I/O interconnect. Test generation and application strategies are proposed by taking into account the limited

A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs

by Srilata Raman Liu , 1996
"... In this paper we present a timing-constrainedrouting algorithm for symmetrical FPGAs which embodies a novel incremental routing strategy that combines global and detailedrouting, and a routing resourceallocation algorithm that takes into account both the characteristics of the routing resources and ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
symmetrical FPGA consists of a 2-D arrayof logic blocks (LBs) surrounded by input-output blocks (IOBs) and a grid of prelaid metal segments that constitute the interconnects [1]. Switch matrices containing n-channel pass transistors (switches) electrically connect adjoining metal segments and connection
Results 1 - 7 of 7