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Leakage Power

by Atluri. Jhansi Rani, K. Harikishore, Fazal Noor Basha, V. G. Santhi Swaroop, L. Veeraraju
"... Abstract- The power consumption is major concern in Very Large Scale Integration (VLSI) circuit design and reduce the power dissipation is challenging job for low power designers.. International technology roadmap for semiconductors (ITRS) reports that “leakage power dissipation ” may come to domina ..."
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Abstract- The power consumption is major concern in Very Large Scale Integration (VLSI) circuit design and reduce the power dissipation is challenging job for low power designers.. International technology roadmap for semiconductors (ITRS) reports that “leakage power dissipation ” may come

Drowsy Caches: Simple Techniques for Reducing Leakage Power

by Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor Mudge - PROC. 29TH INT’L SYMP. COMPUTER ARCHITECTURE , 2002
"... On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. Howev ..."
Abstract - Cited by 251 (1 self) - Add to MetaCart
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage

Leakage Power Estimation in SRAMs

by Mahesh Mamidipaka, Kamal Khouri, Nikil Dutt, Magdy Abadir , 2003
"... In this paper we propose analytical models for estimating the leakage power in CMOS based SRAM designs. We identify the transistors that contribute to the leakage power in each SRAM sub-circuit as a function of the operation (read/write/idle) on the SRAM and develop parameterized leakage power model ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
In this paper we propose analytical models for estimating the leakage power in CMOS based SRAM designs. We identify the transistors that contribute to the leakage power in each SRAM sub-circuit as a function of the operation (read/write/idle) on the SRAM and develop parameterized leakage power

Compilers for Leakage Power Reduction

by Yi-ping You, Chingren Lee, Jenq Kuen Lee - ACM Transactions on Design Automation of Electronic Systems
"... Power leakage constitutes an increasing fraction of the total power consumption in modern semi-conductor technologies. Recent research efforts indicate that architectures, compilers, and software can be optimized so as to reduce the switching power (also known as dynamic power) in micropro-cessors. ..."
Abstract - Cited by 9 (6 self) - Add to MetaCart
Power leakage constitutes an increasing fraction of the total power consumption in modern semi-conductor technologies. Recent research efforts indicate that architectures, compilers, and software can be optimized so as to reduce the switching power (also known as dynamic power) in micropro

Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power

by Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi - in Proceedings of the 28th International Symposium on Computer Architecture , 2001
"... Power dissipation is increasingly important in CPUs ranging from those intended for mobile use, all the way up to highperformance processors for high-end servers. While the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern. Chipmakers expect tha ..."
Abstract - Cited by 280 (26 self) - Add to MetaCart
Power dissipation is increasingly important in CPUs ranging from those intended for mobile use, all the way up to highperformance processors for high-end servers. While the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern. Chipmakers expect

Active Leakage Power Optimization for FPGAs

by Jason H. Anderson, Farid N. Najm, Tim Tuan - FPGA'04 , 2004
"... We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a fundament ..."
Abstract - Cited by 51 (3 self) - Add to MetaCart
We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a

Leakage Power Reduction for Reactive Computation

by Michele Favalli, Cecilia Metra
"... Because of device scaling, leakage power is becoming a consistent fraction of the total power dissipated in CMOS circuits. In particular, it is dominant in reactive systems characterized by burst computations followed by long periods of inactivity. To reduce leakage power during such periods, we ..."
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Because of device scaling, leakage power is becoming a consistent fraction of the total power dissipated in CMOS circuits. In particular, it is dominant in reactive systems characterized by burst computations followed by long periods of inactivity. To reduce leakage power during such periods, we

Leakage Power Reduction in CMOS

by Ruchika Mittal, Sarita Bajaj
"... The advantage of scaling devices is to achieve high performance, low power, large integration and low cost continues to be attractive to the semiconductor industries. However, increasing variability in the device characteristics, soft errors and device degradation in CMOS technologies pose major cha ..."
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The advantage of scaling devices is to achieve high performance, low power, large integration and low cost continues to be attractive to the semiconductor industries. However, increasing variability in the device characteristics, soft errors and device degradation in CMOS technologies pose major

On the Limits of Leakage Power Reduction in Caches

by Yan Meng, Timothy Sherwood, Ryan Kastner - Proc. of Int. Symp. on High-Performance Computer Architecture , 2005
"... If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption. Caches, due to the fact that they account for the largest fraction of on-chip transistors in most modern processors, are a primary candidate for attacking the leakage probl ..."
Abstract - Cited by 23 (2 self) - Add to MetaCart
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption. Caches, due to the fact that they account for the largest fraction of on-chip transistors in most modern processors, are a primary candidate for attacking the leakage

Leakage Power Modeling and Optimization in Interconnection Networks

by Xuning Chen, Li-shiuan Peh - In International Symposium on Low Power Electronics and Design , 2003
"... Power will be the key limiter to system scalability as inter-connection networks take up an increasingly significant por-tion of system power. In this paper, we propose an architec-tural leakage power modeling methodology that achieves 95-98 % accuracy against HSPICE estimates. When applied to inter ..."
Abstract - Cited by 66 (12 self) - Add to MetaCart
Power will be the key limiter to system scalability as inter-connection networks take up an increasingly significant por-tion of system power. In this paper, we propose an architec-tural leakage power modeling methodology that achieves 95-98 % accuracy against HSPICE estimates. When applied
Results 1 - 10 of 3,065