Abstract- The power consumption is major concern in Very Large Scale Integration (VLSI) circuit design and reduce the power dissipation is challenging job for low power designers.. International technology roadmap for semiconductors (ITRS) reports that “leakage power dissipation ” may come

In this paper we propose analytical models for estimating the leakage power in CMOS based SRAM designs. We identify the transistors that contribute to the leakage power in each SRAM sub-circuit as a function of the operation (read/write/idle) on the SRAM and develop parameterized leakage power

On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage

Power leakage constitutes an increasing fraction of the total power consumption in modern semi-conductor technologies. Recent research efforts indicate that architectures, compilers, and software can be optimized so as to reduce the switching power (also known as dynamic power) in micropro

We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a

Power dissipation is increasingly important in CPUs ranging from those intended for mobile use, all the way up to highperformance processors for high-end servers. While the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern. Chipmakers expect

Because of device scaling, leakage power is becoming a consistent fraction of the total power dissipated in CMOS circuits. In particular, it is dominant in reactive systems characterized by burst computations followed by long periods of inactivity. To reduce leakage power during such periods, we

The advantage of scaling devices is to achieve high performance, low power, large integration and low cost continues to be attractive to the semiconductor industries. However, increasing variability in the device characteristics, soft errors and device degradation in CMOS technologies pose major

If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption. Caches, due to the fact that they account for the largest fraction of on-chip transistors in most modern processors, are a primary candidate for attacking the leakage

Power will be the key limiter to system scalability as inter-connection networks take up an increasingly significant por-tion of system power. In this paper, we propose an architec-tural leakage power modeling methodology that achieves 95-98 % accuracy against HSPICE estimates. When applied