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Power Estimation for Large Sequential Circuits
"... Abstract – A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a usersupplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired powe ..."
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Abstract – A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a usersupplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired
Power Estimation for Large Sequential Circuits
"... Abstract – A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a usersupplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired powe ..."
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Abstract – A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a usersupplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired
Accurate Power Estimation for Large Sequential Circuits
 IEEE International Conference on ComputerAided Design
, 1997
"... A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a usersupplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value whi ..."
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Cited by 26 (2 self)
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which can be quite tight (under 10% di#erence between the two in many cases). As a result, the power dissipation is obtained by simulating only a fraction of the potentially very large vector set. 1. Introduction Power dissipation of VLSI circuits is a major concern of the semiconductor industry
Accurate Power Estimation for Large Sequential Circuits †
"... A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a usersupplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value whi ..."
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A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a usersupplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value
Accurate Power Estimation for Large Sequential Circuits †
"... A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a usersupplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value whi ..."
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A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a usersupplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value
Towards the Functional Verification of Large Sequential Circuits
"... Verifying the equivalence of sequential circuits is computationally expensive. Therefore it is interesting to investigate whether a divideandconquer strategy can be used to manage the complexity of this problem. This approach requires a verification method which combines an effective decomposition ..."
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Verifying the equivalence of sequential circuits is computationally expensive. Therefore it is interesting to investigate whether a divideandconquer strategy can be used to manage the complexity of this problem. This approach requires a verification method which combines an effective
An Implicationbased Method to Detect MultiCycle Paths in Large Sequential Circuits
, 2002
"... This paper proposes af2# multicycle path analysis method fz large sequential circuits. It determines whether or not all the paths between every flipflop pair are multicycle paths. The proposed method is based on ATPG techniques, especially on implication techniques, to utilize circuit structure a ..."
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Cited by 3 (1 self)
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This paper proposes af2# multicycle path analysis method fz large sequential circuits. It determines whether or not all the paths between every flipflop pair are multicycle paths. The proposed method is based on ATPG techniques, especially on implication techniques, to utilize circuit structure
An Efficient Solution to the Storage Correspondence Problem For Large Sequential Circuits
"... Abstract Traditional statetraversalbased methods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if the correspondence of the memory elements of the two circuits can be established, a difficult sequential verification ..."
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Abstract Traditional statetraversalbased methods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if the correspondence of the memory elements of the two circuits can be established, a difficult sequential verification
Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits
 Proc. Int. Conf. VLSI Design
, 1997
"... This paper discusses the important role of fault grouping in a parallel 32bit fault simulator such as PROOFS. Three algorithms are presented which dynamically order the fault list during fault simulation to determine how the faults get grouped together. The dynamic fault grouping algorithms were in ..."
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Cited by 3 (0 self)
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incorporated into PROOFS and tested on benchmark circuits. The algorithms showed a marked reduction in the number of faulty circuit gate evaluations (compared to a static fault grouping) for almost all of the circuits with more than 20 flipflops. For the largest benchmark circuit, s35932, all
TechnologyDriven FSM Partitioning for Synthesis of Large Sequential Circuits Targeting Lookup
"... Abstract. Different to common approaches we propose a novel Finite State Machine (FSM) partitioning procedure which takes technologyspecific features into consideration. Moreover, partitioning and state encoding are performed simultaneously. We discuss the method utilizing the technology of Lookup ..."
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Cited by 1 (0 self)
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Table (LUT)based FPGAs in detail. Our implementation can be used as an addon for usual FPGA synthesis systems. We inserted this procedure into the FPGA design flow and achieved average area reductions by 38 % and saved circuit depth by 29 % for large FSM benchmarks. 1
Results 1  10
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