Results 1 - 10 of 397

Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power

by Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi - in Proceedings of the 28th International Symposium on Computer Architecture , 2001
"... Power dissipation is increasingly important in CPUs ranging from those intended for mobile use, all the way up to highperformance processors for high-end servers. While the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern. Chipmakers expect tha ..."
Abstract - Cited by 280 (26 self) - Add to MetaCart
of frequent use when first brought into the cache, and then have a period of “dead time ” before they are evicted. By devising effective, low-power ways of deducing dead time, our results show that in many cases we can reduce L1 cache leakage energy by 4x in SPEC2000 applications without impacting performance

Let Caches Decay: Reducing Leakage Energy via Exploitation of Cache Generational Behavior

by Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi , 2002
"... This paper examines methods for reducing leakage power within the cache memories of the CPU. Because caches comprise much of a CPU chip's area and transistor counts, they are reasonable targets for attacking leakage. We discuss policies and implementations for reducing cache leakage by invalida ..."
Abstract - Cited by 31 (4 self) - Add to MetaCart
" before they are evicted. By devising eective, low-power ways of deducing dead time, our results show that in many cases we can reduce L1 cache leakage energy by 4x in SPEC2000 applications without impacting performance. Because our decay-based techniques have notions of competitive on-line algorithms

Drowsy Caches: Simple Techniques for Reducing Leakage Power

by Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor Mudge - PROC. 29TH INT’L SYMP. COMPUTER ARCHITECTURE , 2002
"... On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. Howev ..."
Abstract - Cited by 251 (1 self) - Add to MetaCart
to our projections, in a 0.07um CMOS process, drowsy caches will be able to reduce the total energy (static and dynamic) consumed in the caches by 50%-75%. We also argue that the use of drowsy caches can simplify the design and control of low-leakage caches, and avoid the need to completely turn off

Leakage Energy Management in Cache Hierarchies

by L. Li, I. Kadayif, Y-f. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, A. Sivasubramaniam , 2002
"... Energy management is important for a spectrum of systems ranging from high-performance architectures to lowend mobile and embedded devices. With the increasing number of transistors, smaller feature sizes, lower supply and threshold voltages, the focus on energy optimization is shifting from dynamic ..."
Abstract - Cited by 26 (4 self) - Add to MetaCart
dynamic to leakage energy. Leakage energy is of particular concern in dense cache memories that form a major portion of the transistor budget. In this work, we present several architectural techniques that exploit the data duplication across the different levels of cache hierarchy. Specifically, we employ

Gated-V dd : A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories

by Michael Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar , 2000
"... Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in onchip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applications. This paper explores an integrated arch ..."
Abstract - Cited by 227 (11 self) - Add to MetaCart
Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in onchip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applications. This paper explores an integrated

The filter cache: An energy efficient memory structure

by Johnson Kin, Munish Gupta, William H. Mangione-smith - In Proceedings of the 1997 International Symposium on Microarchitecture , 1997
"... Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occupy a large portion of the chip area. Not surprisingly, these caches often consume a significant amount of power. In many ..."
Abstract - Cited by 222 (4 self) - Add to MetaCart
applications, such as portable devices, low power is more important than performance. We propose to trade performance for power consumption by filtering cache references through an unusually small L1 cache. An L2 cache, which is similar in size and structure to a typical L1 cache, is positioned behind

LEAKAGE ENERGY REDUCTION IN ON-CHIP MICROPROCESSOR CACHES

by Zhang Chengyi, Zhang Minxuan, Xing Zuocheng
"... Leakage power is becoming dominant part of the micro-processor chip power budget as feature size shrinks. Leakage energy consumption is of particular concern in memory structures, such as on-chip caches, for large scale transistors and rare access. Chipmakers have pro-posed many low leak circuit tec ..."
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with existing LRU information to aggres-sively cut off lines in L1 cache. ADSR (Always Drowsy Speculatively Recover) puts the whole L2 cache in low leakage state all the time and speculatively recovers line’s supply voltage using prefetch-like mechanism. We run SPEC CPU2000 benchmarks on a cycle accurate

An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches

by Se-Hyun Yang, Michael D. Powell , Babak Falsafi, Kaushik Roy , T. N. Vijaykumar , 2001
"... Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold leakage current even when the transistor is ..."
Abstract - Cited by 132 (7 self) - Add to MetaCart
is not switching. Estimates suggest a five-fold increase in leakage energy in every future generation. In modern microarchitectures, much of the leakage energy is dissipated in large on-chip cache memory structures with high transistor densities. While cache utilization varies both within and across applications

Managing Leakage Energy in Cache Hierarchies

by Lin Li, Ismail Kadayif, Yuh-fang Tsai, N. Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin, Anand Sivasubramaniam - Journal of Instruction-level Parallelism , 2003
"... Energy management is important for a spectrum of systems ranging from high-performance architectures to low-end mobile and embedded devices. With the increasing number of transistors, smaller feature sizes, lower supply and threshold voltages, the focus on energy optimization is shifting from dyn ..."
Abstract - Cited by 3 (0 self) - Add to MetaCart
dynamic to leakage energy. In fact, leakage energy is projected to become the dominant portion of the chip power budget for 0.10 micron technology and below. Leakage energy is of particular concern in dense cache memories that form a major portion of the transistor budget.

Using Dead Block Information to Minimize I-cache Leakage Energy Summary

by Mohan G Kabadi, Ranjani Parthasarathi , 2007
"... Power-conscious design using hardware and/or software means has become crucial for both mobile and high performance processors. This paper explores integrated software and circuit level technique to reduce the leakage energy in iL1-cache of high performance microprocessors by eliminating the basic b ..."
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Power-conscious design using hardware and/or software means has become crucial for both mobile and high performance processors. This paper explores integrated software and circuit level technique to reduce the leakage energy in iL1-cache of high performance microprocessors by eliminating the basic
Results 1 - 10 of 397