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1,077
Performance and power impact of issue-width in chip-multiprocessor cores
- In International Conference on Parallel Processing
, 2003
"... In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-threaded and single-threaded applications. This paper explores the trade-off between issue-width of the cores and the number ..."
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Cited by 21 (0 self)
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In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-threaded and single-threaded applications. This paper explores the trade-off between issue-width of the cores and the number
Complexity-effective superscalar processors
- IN PROCEEDINGS OF THE 24TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
, 1997
"... The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are ana-lyzed. Each is modeled and Spice simulated for ..."
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Cited by 467 (5 self)
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for feature sizes of 0:8m, 0:35m, and 0:18m. Performance results and trends are expressed in terms of issue width and window size. Our analysis indicates that window wakeup and selection logic as well as operand bypass logic are likely to be the most critical in the future. A microarchitecture that simplifies
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores
"... This paper explores the trade-off between the issuewidth of the cores and the number of cores on a chip by considering design points with comparable area with respect to both performance and energy. We focus on scalable parallel applications from SPLASH-2. While they are known to benefit from as man ..."
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as many cores as possible we show that these applications can be run as efficiently and with comparable power consumption on a chip-multiprocessor (CMP) with fewer, but wider-issue cores. This is attributable to their inherent ILP and the fact that fewer cores result in less performance and power
Pipeline gating: speculation control for energy reduction
- In Proceedings of the 25th Annual International Symposium on Computer Architecture
, 1998
"... Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although speculative execution is essential for increasing the instructions per cycle (IPC), it does come at a cost. A large amount o ..."
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Cited by 288 (3 self)
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overhead will increase in the future as processors use more aggressive speculation and wider issue widths [9]. In this paper, we present an innovative method for power reduction which, unlike previous work that sacrificed flexibility or performance, reduces power in high-performance microprocessors without
Pyramidal implementation of the Lucas Kanade feature tracker
- Intel Corporation, Microprocessor Research Labs
, 2000
"... grayscale value of the two images are the location x = [x y] T, where x and y are the two pixel coordinates of a generic image point x. The image I will sometimes be referenced as the first image, and the image J as the second image. For practical issues, the images I and J are discret function (or ..."
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Cited by 308 (0 self)
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grayscale value of the two images are the location x = [x y] T, where x and y are the two pixel coordinates of a generic image point x. The image I will sometimes be referenced as the first image, and the image J as the second image. For practical issues, the images I and J are discret function (or
Width parameters beyond tree-width and their applications
- Computer Journal
, 2007
"... Besides the very successful concept of tree-width (see [Bodlaender, H. and Koster, A. (2007) Combinatorial optimisation on graphs of bounded treewidth. These are special issues on Parameterized Complexity]), many concepts and parameters measuring the similarity or dissimilarity of structures compare ..."
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Cited by 40 (0 self)
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Besides the very successful concept of tree-width (see [Bodlaender, H. and Koster, A. (2007) Combinatorial optimisation on graphs of bounded treewidth. These are special issues on Parameterized Complexity]), many concepts and parameters measuring the similarity or dissimilarity of structures
Lx: A Technology Platform for Customizable VLIW Embedded Processing
, 2000
"... Lx is a scalable and customizable VLIW processor technology platform designed by Hewlett-Packard and STMicroelectronics that allows variations in instruction issue width, the number and capabilities of structures and the processor instruction set. For Lx we developed the architecture and software fr ..."
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Cited by 135 (2 self)
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Lx is a scalable and customizable VLIW processor technology platform designed by Hewlett-Packard and STMicroelectronics that allows variations in instruction issue width, the number and capabilities of structures and the processor instruction set. For Lx we developed the architecture and software
Defining Wakeup Width for Efficient Dynamic Scheduling
- in ICCD 2004
, 2004
"... A larger Dynamic Scheduler (DS) exposes more Instruction Level Parallelism (ILP), giving better performance. However, a larger DS also results in a longer scheduler latency and a slower clock speed. In this paper, we propose a new DS design that reduces the scheduler critical path latency by reducin ..."
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Cited by 8 (3 self)
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by reducing the wakeup width (defined as the effective number of results used for instruction wakeup). The design is based on the realization that the average number of results per cycle that are immediately required to wake up the dependent instructions is considerably less than the processor issue width
Space and width in propositional resolution
- Bulletin of the European Association of Theoretical Computer Science
"... Starting with this issue I take over the position of Lance Fortnow as editor of this column. First of all I would like to thank him for his excellent work. He has been able to touch in this column many di erent topics, opening the area and re ecting how broad the eld of computational complexity real ..."
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Cited by 7 (0 self)
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Starting with this issue I take over the position of Lance Fortnow as editor of this column. First of all I would like to thank him for his excellent work. He has been able to touch in this column many di erent topics, opening the area and re ecting how broad the eld of computational complexity
Recommendations to Avoid Short Pulse Width Issues in
"... The High-Voltage Integrated Circuit (HVIC) gate driver family is designed to drive an N-channel MOSFET or IGBT up to 600 V. One of the most common methods to supply power to the high-side gate drive circuitry of the high-voltage ..."
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The High-Voltage Integrated Circuit (HVIC) gate driver family is designed to drive an N-channel MOSFET or IGBT up to 600 V. One of the most common methods to supply power to the high-side gate drive circuitry of the high-voltage
Results 1 - 10
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1,077
