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Table 4 Dynamically reconfigurable parameters and tradeoffs

in Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations
by Prashant Jain, Andrew Laffely, Wayne Burleson, Russell Tessier, Dennis Goeckel
"... In PAGE 30: ... This issue is especially important for multimedia. Table4 presents a summary of varied computational parameters and corresponding observed tradeoffs. The tradeoffs provide valuable information that can be used to develop a hardware controller block.... ..."

Table 1. Reconfiguration time.

in A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary Vectors
by Valery Sklyarov, Iouliia Skliarova, Arnaldo Oliveira, António B. Ferrari 2003
"... In PAGE 7: .... Parallel port of PC for the XC4010XL FPGA. For such purposes we have used the XS40 and XStend boards of XESS linked to the PC parallel port (this implementation was considered just for educational purposes). Table1 shows the time required for dynamic loading of memory blocks with different parameters through the PCI. The working frequency for the used XCV812E FPGA was set to 30 MHz.... ..."
Cited by 3

Table 1. Reconfiguration time

in Architecture of a Reconfigurable Processor for Implementing Search Algorithms over Discrete Matrices
by Valery Sklyarov, Iouliia Skliarova 2003
"... In PAGE 9: ... The results [35] have shown that the utilized universal circuits of reprogrammable FSMs require similar hardware resources and their timing characteristics are comparable with uniquely designed FSM circuits that cannot be reused. Table1 presents the time required for dynamic loading of memory blocks with different parameters through the second port. Table 1.... In PAGE 9: ...The working frequency for the FPGA XCV812E to be used for experiments was set to 30 MHz. The first line of Table1 contains the required time for reloading the segment register, which activates the required group of RAM segments [35,36]. The other lines show the loading time for RAM blocks.... ..."
Cited by 4

Table 1: Phased introduction of the dynamic mode

in Using dynamic optical networking for high-speed access
by Malathi Veeraraghavan A, Dimitris Logothetis B, Xuan Zheng A
"... In PAGE 11: ... However, we note that these benefits could be increased with even greater sharing of resources. In Table1 , we show one potential approach to introducing the dynamic mode of operation in phases. There are mainly two dimensions: the NICs used in end hosts, and the use of signaling protocols in core and access ring ADMs.... ..."

Table 2. Cost of Dynamic Protocol Reconfiguration of Data Channels

in Tailoring Protocols for Dynamic Network Conditions and User Requirements
by R. De Silva, A. Seneviratne
"... In PAGE 7: ... Because the packet containing the SYN flag can be lost, when changing to an unreliable protocol, the first packet correctly received containing the new protocol ID within the packet header, is considered as the packet carrying the SYN flag. A summary of the costs for the different cases of dynamic reconfiguration is shown in Table2 . For reconfiguration to be viable, the cost of the reconfiguration must be balanced by the gains achieved through the new protocol.... In PAGE 8: ...Reconfiguring a protocol, irrespective of the data, as shown in Table2 , there is only a cost of reconfiguration if we are changing from a reliable protocol to an unreliable protocol or to another reliable protocol. 2.... ..."

Table 2. Cost of Dynamic Protocol Reconfiguration of Data Channels

in Tailoring Protocols for Dynamic Network Conditions and User Requirements
by R. De Silva, A. Seneviratne
"... In PAGE 7: ... Because the packet containing the SYN flag can be lost, when changing to an unreliable protocol, the first packet correctly received containing the new protocol ID within the packet header, is considered as the packet carrying the SYN flag. A summary of the costs for the different cases of dynamic reconfiguration is shown in Table2 . For reconfiguration to be viable, the cost of the reconfiguration must be balanced by the gains achieved through the new protocol.... In PAGE 8: ...Reconfiguring a protocol, irrespective of the data, as shown in Table2 , there is only a cost of reconfiguration if we are changing from a reliable protocol to an unreliable protocol or to another reliable protocol. 2.... ..."

Table 1. Status of the availability of various AOP features in our static and dynamic aspect weaving infrastructures

in Unification of Static and Dynamic AOP for Evolution in Embedded Software Systems
by Wasif Gilani, Fabian Scheler, Daniel Lohman, Olaf Spinczyk, Wolfgang Schröder-Preikschat
"... In PAGE 10: ... Table1 gives an overview of the various AOP features currently supported by both our static weaver (AspectC++), and dynamic weaver family. Our dynamic weaver sup- ports more AOP features than any of its counterpart in the C/C++ domain.... ..."

TABLE IV STATIC DECODER VERSUS DYNAMICALLY-RECONFIGURABLE DECODER POWER CONSUMPTION

in A Reconfigurable, Power-Efficient Adaptive Viterbi Decoder
by Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne Burleson 2005
Cited by 3

TABLE IV STATIC DECODER VERSUS DYNAMICALLY-RECONFIGURABLE DECODER POWER CONSUMPTION

in A Reconfigurable, Power-Efficient Adaptive Viterbi Decoder
by Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne Burleson 2005
Cited by 3

Table 1: Support for structure, behavior, and reconfiguration in formal specification approaches for dynamic software architectures

in Supporting Self-Management in Dynamic Software Architecture Specifications
by Jeremy S. Bradbury , James R. Cordy , Juergen Dingel , Michel Wermelinger
"... In PAGE 3: ... There are two approaches that fit this category: c2sadel [17, 21] and Rapide [14, 26]. An overview of the above mentioned approaches can be found in Table1 . A detailed survey using a running example and a compre- hensive description of each approach is given in [4].... ..."
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