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Design and Implementation of the Integer Unit Datapath of the MAP Cluster of the M-Machine
, 1996
"... This thesis presents the design and implementation of the integer unit datapath found in the execution stage of the MAP cluster pipeline. It begins with a discussion of design flow and techniques before presenting the integer unit specification. Next, the integer unit architecture is developed. Fina ..."
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Cited by 1 (0 self)
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This thesis presents the design and implementation of the integer unit datapath found in the execution stage of the MAP cluster pipeline. It begins with a discussion of design flow and techniques before presenting the integer unit specification. Next, the integer unit architecture is developed
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique
"... Abstract — To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (VDD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDD scaling can reduce the energy, the minimu ..."
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at their VDDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum
Integer Unit User’s Manual for Embedded Real time 32–bit Computer (ERC32) for SPACE Applications
, 1998
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Integer Unit User’s Manual for Embedded Real time 32–bit Computer (ERC32) for SPACE Applications
"... ..."
Polynomial time algorithms for multicast network code construction
- IEEE TRANS. ON INFO. THY
, 2005
"... The famous max-flow min-cut theorem states that a source node can send information through a network ( ) to a sink node at a rate determined by the min-cut separating and. Recently, it has been shown that this rate can also be achieved for multicasting to several sinks provided that the intermediat ..."
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Cited by 316 (29 self)
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algorithms for designing linear codes for directed acyclic graphs with edges of unit capacity. We extend these algorithms to integer capacities and to codes that are tolerant to edge failures.
INTEGER
"... details. You are advised to enclose any calls to NAG Parallel Library routines between calls to Z01AAFP and Z01ABFP. 1 Description F04EBFP calculates the solution of a set of real linear equations AX = B or A T X = B, with multiple right-hand sides, using an LU factorization, where A and B are n by ..."
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by n and n by r matrices respectively. The routine first computes an LU factorization of A as A = PLU,wherePis a permutation matrix, L is lower triangular with unit diagonal elements and U is upper triangular. The routine uses partial pivoting, with row interchanges. An approximation to X is found
INTEGER
"... Note: before using this routine, please read the Users ’ Note for your implementation to check for implementation-dependent details. You are advised to enclose any calls to NAG Parallel Library routines between calls to Z01AAFP and Z01ABFP. 1 Description F04EBFP calculates the solution of a set of r ..."
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of real linear equations AX = B or A T X = B, with multiple right-hand sides, using an LU factorization, where A and B are n by n and n by r matrices respectively. The routine first computes an LU factorization of A as A = PLU,wherePis a permutation matrix, L is lower triangular with unit diagonal
INTEGER
"... Note: before using this routine, please read the Users ’ Note for your implementation to check for implementation-dependent details. You are advised to enclose any calls to NAG Parallel Library routines between calls to Z01AAFP and Z01ABFP. 1 Description F04ECFP calculates the solution of a set of c ..."
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of complex linear equations AX = B, A T X = B or A H X = B, with multiple right-hand sides, using an LU factorization, where A and B are n by n and n by r matrices respectively. The routine first computes an LU factorization of A as A = PLU,wherePis a permutation matrix, L is lower triangular with unit
12.7-times Energy Efficiency Increase of 16-bit Integer Unit by Power Supply Voltage (VDD) Scaling from 1.2V to 310mV Enabled by Contention-less Flip-Flops (CLFF
- and Separated VDD between Flip-Flops and Combinational Logics,” IEEE International Symp. Low Power Electronics and Design
, 2011
"... Abstract — Contention-less flip-flops (CLFF’s) and separated power supply voltages (VDD) between flip-flops (FF’s) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a 65 ..."
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Cited by 2 (2 self)
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Abstract — Contention-less flip-flops (CLFF’s) and separated power supply voltages (VDD) between flip-flops (FF’s) and combinational logics are proposed to achieve a maximum energy efficiency operation. The proposed technologies were applied to a 16-bit integer unit (IU) for media processing in a
Maximum Lifetime Routing In Wireless Sensor Networks
- IEEE/ACM TRANSACTIONS ON NETWORKING
, 2000
"... Routing in power-controlled wireless sensor networks is formulated as an optimization problem with the goal of maximizing the system lifetime. Considering that the information is delivered in the form of packets, we identified the problem as an integer programming problem. It is known that the syste ..."
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Cited by 282 (0 self)
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Routing in power-controlled wireless sensor networks is formulated as an optimization problem with the goal of maximizing the system lifetime. Considering that the information is delivered in the form of packets, we identified the problem as an integer programming problem. It is known
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2,193
