Tools
Sorted by:
Try your query at:
 |
 |
 |
 |
 |
 |
Results 1 - 10
of
326
Compiler-directed instruction duplication for soft error detection. Design, Automation and Test in Europe
, 2005
"... Abstract In this work, we experiment with complier-directed instruction duplication to detect soft errors in VLIW datapaths . In the proposed approach, the compiler determines the instruction schedule by balancing the permissible performance degradation with the required degree of duplication. Our ..."
Abstract
-
Cited by 8 (0 self)
- Add to MetaCart
Abstract In this work, we experiment with complier-directed instruction duplication to detect soft errors in VLIW datapaths . In the proposed approach, the compiler determines the instruction schedule by balancing the permissible performance degradation with the required degree of duplication. Our
The Duplication of Content in Instruction Caches and its Performance Implications
, 2005
"... This paper shows that when there is a miss for a block in a cache the required block of data may reside already in the cache but under a different tag. We refer to this phenomenon as Cache-Content-Duplication. This report characterizes cache-content-duplication for instruction caches and investigate ..."
Abstract
-
Cited by 1 (1 self)
- Add to MetaCart
This paper shows that when there is a miss for a block in a cache the required block of data may reside already in the cache but under a different tag. We refer to this phenomenon as Cache-Content-Duplication. This report characterizes cache-content-duplication for instruction caches
Dynamically Detecting Cache-Content-Duplication in Instruction Caches
, 2007
"... Cache-content-duplication (CCD) occurs when there is a miss for a block in a cache and the entire content of the missed block is already in the cache in a block with a different tag. Caches aware of content-duplication can have smaller miss penalty by fetching, on a miss to a duplicate block, direct ..."
Abstract
- Add to MetaCart
and that an idealized duplication-detection mechanism for instruction caches has the potential to increase performance of an out-of-order processor, with a 2-way eight instruction per block 16KB instruction cache, often by more than 5 % and up to 20%. This work also proposes CATCH, a hardware based mechanism
Hyperthreading technology architecture and microarchitecture.
- Intel Technical Journal,
, 2002
"... ABSTRACT Intel's Hyper-Threading Technology brings the concept of simultaneous multi-threading to the Intel Architecture. Hyper-Threading Technology makes a single physical processor appear as two logical processors; the physical execution resources are shared and the architecture state is dup ..."
Abstract
-
Cited by 182 (1 self)
- Add to MetaCart
is duplicated for the two logical processors. From a software or architecture perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on multiple physical processors. From a microarchitecture perspective, this means that instructions from
ED 4 I: Error detection by diverse data and duplicated instructions
- In IEEE Transactions on Computers
, 2002
"... AbstractÐErrors in computing systems can cause abnormal behavior and degrade data integrity and system availability. Errors should be avoided especially in embedded systems for critical applications. However, as the trend in VLSI technologies has been toward smaller feature sizes, lower supply volta ..."
Abstract
-
Cited by 8 (2 self)
- Add to MetaCart
fault tolerance �SIHFT), low cost fault tolerance, concurrent error detection, data diversity, duplicated instructions. 1
Instruction Precomputation with Memoization for Fault Detection
"... Abstract—Fault tolerance (FT) has become a major concern in computing systems. Instruction duplication has been proposed to verify application execution at run time. Two techniques, instruction memoization and precomputation, have been shown to improve the performance and fault coverage of duplicati ..."
Abstract
- Add to MetaCart
Abstract—Fault tolerance (FT) has become a major concern in computing systems. Instruction duplication has been proposed to verify application execution at run time. Two techniques, instruction memoization and precomputation, have been shown to improve the performance and fault coverage
Comparing Tail Duplication with Compensation Code in Single Path Global Instruction
- in Proceedings of the 9th International Conference on Compiler Construction (CC 2001
, 2001
"... Global instruction scheduling allows operations to move across basic block boundaries to create tighter schedules. When operations move above control flow joins, some code duplication is generally necessary to preserve semantics. Tail duplication and compensation code are approaches to duplicati ..."
Abstract
-
Cited by 1 (0 self)
- Add to MetaCart
Global instruction scheduling allows operations to move across basic block boundaries to create tighter schedules. When operations move above control flow joins, some code duplication is generally necessary to preserve semantics. Tail duplication and compensation code are approaches
into Instructional Strategies
, 2005
"... This document may be used for private study or research purpose only. This document or any part of it may not be duplicated and/or distributed without permission of the copyright owner. The Singapore Copyright Act applies to the use of this document. ..."
Abstract
- Add to MetaCart
This document may be used for private study or research purpose only. This document or any part of it may not be duplicated and/or distributed without permission of the copyright owner. The Singapore Copyright Act applies to the use of this document.
Cache-Content- Duplication for Valid Blocks
"... Cache-content-duplication (CCD) occurs when there is a miss for a block in a cache and the content of the missed block resides already in the cache but under a different tag. Caches aware of contentduplication can have smaller miss penalty by fetching, on a miss to a duplicate block, directly from t ..."
Abstract
- Add to MetaCart
examines the potential of CCD for instruction caches at the granularity of valid blocks. We show that CCD is a frequent phenomenon and that an idealized duplication-detection mechanism for instruction caches has the potential to increase performance of an out-of-order processor, with a 2-way eight
Instruction Copyright
"... Compliance The board recognizes that federal law makes it illegal to duplicate copyrighted materials without authorization of the holder of the copyright, except for certain exempt purposes. Severe penalties may be imposed for unauthorized copying or using of audiovisual or printed materials and com ..."
Abstract
- Add to MetaCart
Compliance The board recognizes that federal law makes it illegal to duplicate copyrighted materials without authorization of the holder of the copyright, except for certain exempt purposes. Severe penalties may be imposed for unauthorized copying or using of audiovisual or printed materials
Results 1 - 10
of
326
