Abstract not found

rate that can be used to simplify the process of buffer pool sizing. Since the buffer replacement algorithm determines the buffer hit rate, we model the replacement algorithm which, in the case of DB2/UDB, is a variation of the GCLOCK algorithm. A Markov Chain model of GCLOCK is used to estimate

The problem of spurious apparent patterns arising by chance is a fundamental one for pattern detection. Classical approaches, based on adjustments such as the Bonferroni procedure, are arguably not appropriate in a data mining context. Instead, methods based on the false discovery rate

Clusters of identical intermediate servers are often created to improve availability and robustness in many domains. The use of proxy servers for the WWW and of Rendezvous Points in multicast routing are two such situations. However, this approach can be inefficient if identical requests are received and processed by multiple servers. We present an analysis of this problem, and develop a method called the Highest Random Weight (HRW) Mapping that eliminates these difficulties. Given an object name and a set of servers, HRW maps a request to a server using the object name, rather than any a priori knowledge of server states. Since HRW always maps a given object name to the same server within a given cluster, it may be used locally at client sites to achieve consensus on objectserver mappings. We present an analysis of HRW and validate it with simulation results showing that it gives faster service times than traditional request allocation schemes such as round-robin or least-loaded, and...

cache, hit rate, estimation, LRU stack distance, success function * Internal Accession Date Only This paper considers the problem of inferring cache hit rates from observations of references that miss in the cache. In the Web context, this is the problem of inferring a browser's cache hit rate

efficiently. With these new rotated features our sample face detector shows off on average a 10 % lower false alarm rate at a given hit rate. We also present a novel post optimization procedure for a given boosted cascade improving on average the false alarm rate further by 12.5%. 1

, the content-providers can now allow the proxies to serve multiple clients with different ads from the same cached data stream. In this manner, proxybased ad insertion improves cache hit rates. We begin by describing the problems generated by the use of cache-busting techniques today. We will then describe

This brief note points out something obvious--- something the authors "knew" without really understanding. With apologies to those who did understand, we offer it to those others who, like us, missed the point. We all know that the rate of improvement in microprocessor speed exceeds

Abstract not found

Most of the prior compiler based data locality optimization works target exclusively cache locality optimization, and row-buffer locality in DRAM banks received much less atten-tion. In particular, to the best of our knowledge, there is no single compiler based approach that can improve row-buffer locality in executing irregular applications. This presents a critical problem considering the fact that executing irregu-lar applications in a power and performance efficient man-ner will be a key requirement to extract maximum bene-fits from emerging multicore machines and exascale systems. Motivated by these observations, this paper makes the fol-lowing contributions. First, it presents a compiler-runtime cooperative data layout optimization approach that takes as input an irregular program that has already been opti-mized for cache locality and generates an output code with the same cache performance but better row-buffer locality (lower number of row-buffer misses). Second, it discusses a more aggressive strategy that sacrifices some cache perfor-mance in order to further improve row-buffer performance (i.e., it trades cache performance for memory system per-formance). The ultimate goal of this strategy is to find the right tradeoff point between cache performance and row-buffer performance so that the overall application perfor-mance is improved. Third, the paper performs a detailed evaluation of these two approaches using both an AMD Opteron based multicore system and a multicore simulator. The experimental results, collected using five real-world ir-regular applications, show that (i) conventional cache opti-mizations do not improve row-buffer locality significantly; (ii) our first approach achieves about 9.8 % execution time improvement by keeping the number of cache misses the same as a cache-optimized code but reducing the number of row-buffer misses; and (iii) our second approach achieves even higher execution time improvements (13.8 % on aver-age) by sacrificing cache performance for additional memory performance.