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Guide to Elliptic Curve Cryptography

by Aleksandar Jurisic, Alfred J. Menezes , 2004
"... Elliptic curves have been intensively studied in number theory and algebraic geometry for over 100 years and there is an enormous amount of literature on the subject. To quote the mathematician Serge Lang: It is possible to write endlessly on elliptic curves. (This is not a threat.) Elliptic curves ..."
Abstract - Cited by 610 (18 self) - Add to MetaCart
aim to give the reader an introduction to elliptic curve cryptosystems, and to demonstrate why these systems provide relatively small block sizes, high-speed software and hardware implementations, and offer the highest strength-per-key-bit of any known public-key scheme.

Vogels, U-Net: a user-level network interface for parallel and distributed computing, in:

by Anindya Basu , Vineet Buch , Werner Vogels , Thorsten Von Eicken - Proceedings of the 15th ACM Symposium on Operating System Principles, ACM, , 1995
"... Abstract The U-Net communication architecture provides processes with a virtual view of a network device to enable user-level access to high-speed communication devices. The architecture, implemented on standard workstations using off-the-shelf ATM communication hardware, removes the kernel from th ..."
Abstract - Cited by 597 (17 self) - Add to MetaCart
Abstract The U-Net communication architecture provides processes with a virtual view of a network device to enable user-level access to high-speed communication devices. The architecture, implemented on standard workstations using off-the-shelf ATM communication hardware, removes the kernel from

Algorithms for Scalable Synchronization on Shared-Memory Multiprocessors

by John M. Mellor-crummey, Michael L. Scott - ACM Transactions on Computer Systems , 1991
"... Busy-wait techniques are heavily used for mutual exclusion and barrier synchronization in shared-memory parallel programs. Unfortunately, typical implementations of busy-waiting tend to produce large amounts of memory and interconnect contention, introducing performance bottlenecks that become marke ..."
Abstract - Cited by 573 (32 self) - Add to MetaCart
Busy-wait techniques are heavily used for mutual exclusion and barrier synchronization in shared-memory parallel programs. Unfortunately, typical implementations of busy-waiting tend to produce large amounts of memory and interconnect contention, introducing performance bottlenecks that become

High-Speed MARS Hardware

by Akashi Satoh, Nobuyuki Ooba, Kohji Takano, Edward D'Avignon - In The Third Advanced Encryption Standard Candidate Conference , 2000
"... . High-speed MARS encryption/decryption hardware was developed using a 0.18m IBM CMOS technology. In order to boost performance, a special adder and multiplier was designed by optimizing the adder block structure and interconnections between adder cells using signal delay profiles. A description of ..."
Abstract - Cited by 2 (0 self) - Add to MetaCart
. High-speed MARS encryption/decryption hardware was developed using a 0.18m IBM CMOS technology. In order to boost performance, a special adder and multiplier was designed by optimizing the adder block structure and interconnections between adder cells using signal delay profiles. A description

VL2: Scalable and Flexible Data Center Network”,

by Albert Greenberg , James R Hamilton , Navendu Jain , Srikanth Kandula , Changhoon Kim , Parantap Lahiri , David A Maltz , Parveen Patel , Sudipta Sengupta - ACM SIGCOMM Computer Communication Review, , 2009
"... Abstract To be agile and cost e ective, data centers should allow dynamic resource allocation across large server pools. In particular, the data center network should enable any server to be assigned to any service. To meet these goals, we present VL, a practical network architecture that scales t ..."
Abstract - Cited by 461 (12 self) - Add to MetaCart
leverages proven network technologies, already available at low cost in high-speed hardware implementations, to build a scalable and reliable network architecture. As a result, VL networks can be deployed today, and we have built a working prototype. We evaluate the merits of the VL design using

HLA RTI Performance in High Speed LAN Environments

by Richard Fujimoto, Richard Fujimoto Phd, Peter Hoare, Worcs Uk Wr Ps , 1998
"... : This paper presents recent results concerning the realization of HLA RTIs in high-speed LAN environments. Specifically, the UK-RTI and a second, simplified RTI implementation were realized on a cluster of Sun workstations using Myrinet, a gigabit, low-latency interconnection switch developed by My ..."
Abstract - Cited by 11 (2 self) - Add to MetaCart
on high-speed interconnection hardware. Results of this study demonstrate the technical feasibility and performance that can be obtained by exploiting high performance interconnection hardware and software in realizing HLA RTIs. In particular, in most experiments the RTIs using Myrinet achieved one to two

Simulation of High-Speed Interconnects

by Ramachandra Achar, Michel S. Nakhla - PROC. IEEE, MAY 2001 , 2001
"... With the rapid developments in very large-scale integration (VLSI) technology, design and computer-aided design (CAD) techniques, at both the chip and package level, the operating fre-quencies are fast reaching the vicinity of gigahertz and switching times are getting to the subnanosecond levels. Th ..."
Abstract - Cited by 61 (3 self) - Add to MetaCart
. The ever increasing quest for high-speed applications is placing higher demands on interconnect performance and highlighted the previously negligible effects of interconnects, such as ringing, signal delay, distortion, reflections, and crosstalk. In this review paper, various high-speed interconnect

Efficient Fair Queuing using Deficit Round Robin

by M. Shreedhar, George Varghese - SIGCOMM '95 , 1995
"... Fair queuing is a technique that allows each flow passing through a network device to have a fair share of network resources. Previous schemes for fair queuing that achieved nearly perfect fairness were expensive to implement: specifically, the work required to process a packet in these schemes was ..."
Abstract - Cited by 359 (4 self) - Add to MetaCart
was O(log(n)), where n is the number of active flows. This is expensive at high speeds. On the other hand, cheaper approximations of fair queuing that have been reported in the literature exhibit unfair behavior. In this paper, we describe a new approximation of fair queuing, that we call Deficit Round

Geometry Compression

by Michael Deering
"... This paper introduces the concept of Geometry Compression, allowing 3D triangle data to be represented with a factor of 6 to 10 times fewer bits than conventional techniques, with only slight losses in object quality. The technique is amenable to rapid decompression in both software and hardware imp ..."
Abstract - Cited by 350 (0 self) - Add to MetaCart
This paper introduces the concept of Geometry Compression, allowing 3D triangle data to be represented with a factor of 6 to 10 times fewer bits than conventional techniques, with only slight losses in object quality. The technique is amenable to rapid decompression in both software and hardware

The Stanford FLASH multiprocessor

by Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John Hennessy - In Proceedings of the 21st International Symposium on Computer Architecture , 1994
"... The FLASH multiprocessor efficiently integrates support for cache-coherent shared memory and high-performance message passing, while minimizing both hardware and software overhead. Each node in FLASH contains a microprocessor, a portion of the machine’s global memory, a port to the interconnection n ..."
Abstract - Cited by 349 (20 self) - Add to MetaCart
The FLASH multiprocessor efficiently integrates support for cache-coherent shared memory and high-performance message passing, while minimizing both hardware and software overhead. Each node in FLASH contains a microprocessor, a portion of the machine’s global memory, a port to the interconnection
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