the use of PLX's architectural features with four frequently used multimedia kernels: discrete cosine transform, pixel padding, clip test and median filter. Our performance results show that a 64-bit PLX implementation achieves significant speedups compared to a basic 64-bit RISC processor and to IA

Concurrent increases in network bandwidths and processor speeds have created a performance bottleneck at the workstation-to-network host interface . This is especially true for BISDN networks where the fixed length ATM cell is mismatched with application requirements for data transfer; a successful

in the design of the later simulator and other software tools. 2.5.7 Other Issues Both technological and architectural improvements to conventional RISC processors have been progressing at a phenomenal rate. The resulting performance is considerable and still improving rapidly, with techniques such as "

, in addition, simulated cache hit rates. We collected statistics about the inherent data-locality characteristics of these programs and our ability to improve their locality. Performance improvements were difficult to achieve because benchmark programs typically have high hit rates; however, our optimizations

IBM's NorthStar superscalar RISC microprocessor integrates high-bandwith and short pipe depth with low latency and zero cycle branch mispredict penalty into a fully scalable 64-bit PowerPC-compatible symmetric multiprocessor (SMP) implementation. Based on PowerPC architecture, the first

The author has written a package of Fortran routines that perform a variety of arithmetic operations and transcendental functions on floating point numbers of arbitrarily high precision, including large integers. This package features (1) virtually universal portability, (2) high performance

interface is used to leverage the workstation CPU, relieving it of tasks that it performs poorly such as rapid context switching and low-level bit manipulation. The reconfigurable interface handles control of external devices, high-performance input (16 MB/s) and data preformatting. The workstation CPU, a

reported optimizations focus on finite fields of the form GF (p) and GF (2 m), an OEF is the class of fields GF (p m), for p a prime of special form and m a positive integer. Modern RISC workstation processors are optimized to perform integer arithmetic on integers of size up to the word size

Performance aspects of a Lagrangian relaxation based heuristic for solving large 0-1 integer linear programs are discussed. In particular, we look at its application to airline and railway crew scheduling problems. We present a scalable parallelization of the original algorithm used

presents the architecture, data path and instruction set (IS) of the RISC processor. The 64-bit processors, on the other hand, can address enormous amounts of memory up to 16 Exabyte‟s. The proposed design can find its applications in high configured robotic work-stations such as, portable pong gaming kits