A family of high-performance 64-bit RISC workstations and servers based on the new Digital Alpha AXP architecture is described. The hardware implementation uses the powerful new DECchip 21064 CPU and employs a sophisticated new system interconnect structure to achieve the necessary high bandwidth

be minimized by deploying a kernel agent called a packet filter, which discards unwanted packets as early as possible. The original Unix packet filter was designed around a stack-based filter evaluator that performs sub-optimally on current RISC CPUs. The BSD Packet Filter (BPF) uses a new, registerbased

-point support as optional coprocessor instructions, without emphasizing high performance. In 1989, driven by the performance needs of the HP9000 technical workstation line, PA-RISC 1.1 was introduced. This included additional floating-point capabilities, such as more floating-point registers, doubling

this report is to survey a number of leading RISC processors which are deployed in off the shelf scientific workstations, and in some cases massively parallel multi-computers. 1 Introduction

commercially available microprocessor in the world as of January 1995. It contains a quad-issue, superscalar instruction unit; two 64-bit integer execution pipelines; two 64-bit floating-point execution pipelines; and a high-performance memory subsystem with multiprocessor-coherent write-back caches. OVERVIEW

flexible, scalable and high performance routers architecture. A solution to this problem is to use specialized processors, called network processors (NPs). These application specific instruction processors (ASIPs) are specially tailored to perform packet processing operations and

IBM's new POWER3 microprocessor integrates the high-bandwidth and floating point capabilities of its POWER2 architecture predecessor into a fully scaleable 64-bit PowerPC* symmetric multi-processor (SMP) implementation. Based on PowerPC Architecture*, this microprocessor contains

In the last few years the computational power of general-purpose machines has dramatically increased; furthermore high performance workstations quite often offer multimedial capabilities. Therefore it is now possible to implement automatic Speech Recognizers (SRs) without dedicated hardware devices

In the last few years the computational power of general-purpose machines has dramatically increased; furthermore high performance workstations quite often offer multimedial capabilities. Therefore it is now possible to implement automatic Speech Recognizers (SRs) without dedicated hardware devices

Digital's first RISC system built using the 64-bit Alpha AXP architecture is the prototype known as the Alpha demonstration unit or ADU. It consists of a backplane containing 14 slots, each of which can hold a CPU module, a 64MB storage module, or a module containing two 50MB/s I/O channels. A