, motivated by these requirements. The system is called RAGE, and incorporates operating-system style services that permit sophisticated and high level operations on circuits. 1 Introduction Dynamic reconfiguration of FPGAs has recently become viable with the introduction of devices that allow high speed

processor itself. With direct access to the host processor’s register file, the system enables the creation of multi-operand instructions and a speculative execution model key to high-performance, general-purpose reconfigurable computing. Chimaera also supports multi-output functions and utilizes partial

Recen t gen ration s of high-den ity an high-speed FPGAs provide a su#cien t capacity for implemen tin g complete conq urable systemson a chip (CSoCs). Hybrid CPUs that combin e stanZ rd CPU cores withrecon figurable coprocessors are an importan t subclass of CSoCs. With partial y reconfigurable

are fundamental to any Data Grid: reliable, high-speed transport and replica management. Our high-speed transport service, GridFTP, extends the popular FTP protocol with new features required for Data Grid applications, such as striping and partial file access. Our replica management service integrates a replica

Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet processing circuits on this platform are implemented as Dynamic Hardware Plugin (DHP) modules that fit within a specific

Artificial neural network paradigms have shown the capabilities of performing input-output mapping operations even where the transformation rules are not formally defined, are partially known, or are ill-defined. For high speed processing of such information, hardware implementation sarerequired

DSP Application needs to speed-up in computation time can be achieved by assigning complex computation intensive tasks to hardware and by exploiting the parallelism in algorithms. These applications need high performance as well as cost efficient design. Reconfigurable systems offer us potential

Abstract — An efficient high-speed VLSI implementation of the Discrete Wavelet Transform (DWT) based on hardware-efficient parallel FIR filters has been proposed in this paper. High speed 2-D DWT with low computational speed and high throughput with controlled increase of hardware cost is proposed

In this thesis a generic approach for integrating a dynamically recon-figurable device into a general purpose system interconnected with a high-speed interconnect, is described. The system dynamically installs and executes hardware instances implementing functions to accelerate parts of a

in the FPGAs are not balanced appropriately for high-speed operation, (2) FPGA CAD does not automatically provide the requisite transforms to support this operation, and (3) interconnect delays can be large and vary almost continuously, complicating high frequency mapping. We introduce a novel reconfigurable